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| 型號(hào)： | MC68HC05F8B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.8 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | PLASTIC, SDIP-56 |
| 文件頁(yè)數(shù)： | 76/126頁(yè) |
| 文件大小： | 1084K |
| 代理商： | MC68HC05F8B |
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MC68HC05F8
MOTOROLA
6-5
TIMERS
6
corresponding input edge bit (IEDG). Reset does not affect the contents of the Input Capture
register.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronization. Resolution is zero or one count of the free-running counter,
which is 4xRTB internal bus clock cycles.
The free-running counter contents are transferred to the Input Capture register on each valid
signal transition whether the input capture ag (ICF) is set or clear. The Input Capture register
always contains the free-running counter value that corresponds to the most recent input
capture.After a read of the input capture register MSB ($1A), the counter transfer is inhibited until
the LSB ($1B) is also read. This characteristic causes the time used in the input capture software
routine and its interaction with the main program to determine the minimum pulse period. A read
of the input capture register LSB ($1B) does not inhibit the free-running counter transfer since they
occur on opposite edges of the internal bus clock.
6.1.4
Timer Control Register (TCR)
The TCR is a read/write register containing ve control bits. Three bits control interrupts
associated with the three ag bits found in the timer status register (discussed below). The other
two bits control: 1) which edge is signicant to the input capture edge detector (i.e., negative or
positive), and 2) the next value to be clocked to the Output Level registers in response to a
successful output compare. The Timer Control register and the free-running counter are the only
sections of the timer affected by reset. The TCMP pin is forced low during external reset and stays
low until a valid compare changes them to high. Denition of each bit is as follows:
ICIE - Input Capture Interrupt Enable
1 (set)
–
Input Capture interrupt enabled.
0 (clear) –
Input Capture interrupt disabled.
OCIE - Output Compare Interrupt Enable
1 (set)
–
Output Compare interrupt enabled.
0 (clear) –
Output Compare interrupt disabled.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on Reset
$18
ICIE
OCIE
TOIE
0
IEDG
OLVL
0000 00u0
TPG
51
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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