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| 型號(hào)： | MC68HC05F4CDW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 89/130頁(yè) |
| 文件大?。?/td> | 10504K |
| 代理商： | MC68HC05F4CDW |
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MC68HC05F4
6-11
16-BIT PROGRAMMABLE TIMER
6
6.4
Output compare
‘Output compare’ is a technique which may be used, for example, to generate an output waveform,
or to signal when a specic time period has elapsed, by presetting the output compare register to
the appropriate value.
There are two output compare registers: output compare register 1 (OCR1) and output compare
register 2 (OCR2).
There are two output compare interrupt enable bits (OC1IE and OC2IE).
6.4.1
Output compare register 1 (OCR1)
The 16-bit output compare register 1 is made up of two 8-bit registers at locations $0022 (MSB)
and $0023 (LSB). The contents of the output compare register 1 are compared with the contents
of the free-running counter continually and, if a match is found, the corresponding output compare
ag (OC1F) in the timer status register is set. If the timer compare output enable bit (CO1E) is set,
the output level (OLVL1) is transferred to pin TCMP1. The output compare register 1 values and
the output level bit should be changed after each successful comparison to establish a new
elapsed timeout. An interrupt can also accompany a successful output compare provided the
corresponding interrupt enable bit (OC1IE) is set. (The free-running counter is updated every four
internal bus clock cycles.)
After a processor write cycle to the output compare register 1 containing the MSB ($0022), the
output compare function is inhibited until the LSB ($0023) is also written. The user must write both
bytes (locations) if the MSB is written rst. A write made only to the LSB ($0023) will not inhibit the
compare 1 function. The processor can write to either byte of the output compare register 1 without
affecting the other byte. If the timer compare output enable bit (CO1E) is set, the output level
(OLVL1) bit is clocked to the output level register and hence to the TCMP1 pin whether the output
compare ag 1 (OC1F) is set or clear. The minimum time required to update the output compare
register 1 is a function of the program rather than the internal hardware. Because the output
compare ag 1 and the output compare register 1 are not dened at power on, and not affected
by reset, care must be taken when initializing output compare functions with software. The
following procedure is recommended:
–
Write to output compare 1 high to inhibit further compares;
–
Read the timer status register to clear OC1F (if set);
–
Write to output compare 1 low to enable the output compare 1 function.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Output compare 1 high (OCR1H)
$0022
Undened
Output compare 1 low (OCR1L)
$0023
Undened
TPG
57
05F4Book Page 11 Tuesday, August 5, 1997 1:10 pm
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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