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參數(shù)資料
| 型號(hào)： | MC68HC05F4CDW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 117/130頁(yè) |
| 文件大小： | 10504K |
| 代理商： | MC68HC05F4CDW |
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MC68HC05F4
9-5
CPU CORE AND INSTRUCTION SET
9
9.2.6
Tables
Tables for all the instruction types listed above follow. In addition there is a complete alphabetical
listing of all the instructions (see Table 9-7), and an opcode map for the instruction set of the
M68HC05 MCU family (see Table 9-8).
9.3
Addressing modes
Ten different addressing modes provide programmers with the exibility to optimize their code for
all situations. The various indexed addressing modes make it possible to locate data tables, code
conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are
single byte instructions; the longest instructions (three bytes) enable access to tables throughout
memory. Short absolute (direct) and long absolute (extended) addressing are also included. One
or two byte direct addressing instructions access all data bytes in most applications. Extended
addressing permits jump instructions to reach all memory locations.
The term ‘effective address’ (EA) is used in describing the various addressing modes. The
effective address is dened as the address from which the argument for an instruction is fetched
or stored. The ten addressing modes of the processor are described below. Parentheses are used
to indicate ‘contents of’ the location or register referred to. For example, (PC) indicates the
contents of the location pointed to by the PC (program counter). An arrow indicates ‘is replaced
by’ and a colon indicates concatenation of two bytes. For additional details and graphical
illustrations,
refer
to
the
M6805
HMOS/M146805
CMOS
Family
Microcomputer/
Microprocessor User's Manual or to the M68HC05 Applications Guide.
Table 9-1 MUL instruction
Operation
X:A
← X*A
Description
Multiplies the eight bits in the index register by the eight
bits in the accumulator and places the 16-bit result in the
concatenated accumulator and index register.
Condition
codes
H : Cleared
I : Not affected
N : Not affected
Z : Not affected
C : Cleared
Source
MUL
Form
Addressing mode
Cycles
Bytes
Opcode
Inherent
11
1
$42
TPG
83
05F4Book Page 5 Tuesday, August 5, 1997 1:10 pm
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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