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| 型號(hào)： | MC68HC05F4CDW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 86/130頁(yè) |
| 文件大小： | 10504K |
| 代理商： | MC68HC05F4CDW |
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MC68HC05F4
6-9
16-BIT PROGRAMMABLE TIMER
6
6.3
Input capture
‘Input capture’ is a technique whereby an external signal is used to trigger a read of the free
running counter. In this way it is possible to relate the timing of an external signal to the internal
counter value, and hence to elapsed time.
There are two input capture registers: input capture register 1 (ICR1) and input capture register 2 (ICR2).
There are two input capture interrupt enable bits (IC1IE and IC2IE).
6.3.1
Input capture register 1 (ICR1)
The two 8-bit registers that make up the 16-bit input capture register 1 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit 1 senses
a valid transition at TCAP1. The level transition that triggers the counter transfer is dened by the
input edge bit (IEDG1). When an input capture 1 occurs, the corresponding ag IC1F in TSR is
set. An interrupt can also accompany an input capture 1 provided the IC1IE bit in TCR1 is set. The
8 most signicant bits are stored in the input capture register 1 high at $0020, the 8 least
signicant bits in the input capture register 1 low at $0021.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register 1 on each valid signal transition whether the input capture 1 ag (IC1F) is set or
clear. The input capture register 1 always contains the free-running counter value that
corresponds to the most recent input capture 1. After a read of the input capture register 1 MSB
($0020), the counter transfer is inhibited until the LSB ($0021) is also read. This characteristic
causes the time used in the input capture software routine and its interaction with the main
program to determine the minimum pulse period. A read of the input capture register 1 LSB
($0021) does not inhibit the free-running counter transfer since the two actions occur on opposite
edges of the internal bus clock.
Reset does not affect the contents of the input capture register 1, except when exiting STOP mode
(see Section 6.5).
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Input capture 1 high (ICR1H)
$0020
Undened
Input capture 1 low (ICR1L)
$0021
Undened
TPG
55
05F4Book Page 9 Tuesday, August 5, 1997 1:10 pm
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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