參數(shù)資料
型號: MC68HC05F4CDW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 102/130頁
文件大?。?/td> 10504K
代理商: MC68HC05F4CDW
MC68HC05F4
7-7
DTMF/MELODY GENERATOR
7
TGER, TGEC — Tone generation enable for row and column paths
When both bits are held low, the DMG is disabled by forcing the two frequency counters and the
two PLA scanning counters to their reset states. The DMG should then consume zero dynamic
power, if the TNOE bit is also cleared.
When a TGE bit for a path is held high (provided that the value in the frequency control register
for that path is legal), the generator is enabled. All the counters associated with that path are then
run from their reset states.
The reset state of a frequency counter denes the time=0 state of the time step, whereas at their
reset state, the PLA scanning counters, scanning the memory location, contain the dc values of
the staircase sine wave.
In DTMF dialling, the row and column tone values are rst entered to the FCR and FCC registers.
The TGER and TGEC bits are then set or reset simultaneously to achieve dual tone multiple
frequency. Similarly, in melody generation, one path is chosen as the high part, and the other as
the low part. The TGER and TGEC bits are then set and reset according to the rhythm required by
the musical piece. One can exhibit only single tone melody by disabling either TGER or TGEC
permanently. The DTMF column and row frequency tones can also be output separately for testing
by enabling just the one path.
7.4
Operation of the DMG
The DMG is recommended to be operated using the following procedures:
To operate melody generation, the choice of sine wave or square wave output mode is totally up
to the user’s taste. The sine wave melody has a sound like a ute, whereas the square wave
melody possesses much richer harmonics. The required tones are selected through the FCR and
FCC registers. The selected tone is output when the corresponding TGER or TGEC bit and TNOE
bit are set. The FCR register should contain the value representing the tone output frequency and
the FCC register should contain a value of $04 or greater to ensure the output is not blocked by
the data validator.
Table 7-4 Effect of tone generation on DMG
TGER
TGEC
Row Path
Column
Path
0
off
0
1
off
active
1
0
active
off
1
active
TPG
69
05F4Book Page 7 Tuesday, August 5, 1997 1:10 pm
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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