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參數(shù)資料
| 型號： | MC68HC05E6VDWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 85/140頁 |
| 文件大?。?/td> | 1141K |
| 代理商： | MC68HC05E6VDWR2 |
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Core Timer
Core timer registers
MC68HC05E6 — Rev. 1.0
MOTOROLA
Core Timer
49
5-ctimer
CTOFE — Core timer overflow interrupt enable
1 = A core timer overflow interrupt will be generated if CTOF is set
and the I-bit in the CCR is clear.
0 = No core timer overflow interrupt will be generated regardless of
the state of the CTOF flag and the I-bit.
RTIE — Real time interrupt enable
1 = A real time interrupt will be generated if RTIF is set and the I-bit
in the CCR is clear.
0 = No real time interrupt will be generated regardless of the state
of the RTIF flag and the I-bit.
RCTOF — Reset core timer overflow flag
This bit always reads as zero. Writing a ‘1’ to the RCTOF bit clears the
timer overflow flag. Writing a ‘0’ to it has no effect.
RRTIF — Reset real time interrupt flag
This bit always reads as zero. Writing a ‘1’ to the RRTIF bit clears the
real time interrupt flag. Writing a ‘0’ to it has no effect.
RT1, T0 — Real time interrupt rate select
These two bits select one of four taps from the real time interrupt
circuitry. Reset sets both RT0 and RT1 to one, selecting the lowest
periodic rate and therefore the maximum time in which to alter them if
necessary. The COP reset times are also determined by these two
bits. Care should be taken when altering RT0 and RT1 if a timeout is
imminent, or if the timeout period is uncertain. If the selected tap is
modified during a cycle in which the counter is switching, an RTIF
could be missed or an additional one could be generated. To avoid
problems, the COP should be cleared before changing the RTI taps.
See Table 8 for some example RTI periods.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05F32CPU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
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