參數(shù)資料
型號(hào): MC68HC05E6VDWR2
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁(yè)數(shù): 6/140頁(yè)
文件大?。?/td> 1141K
代理商: MC68HC05E6VDWR2
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Central Processing Unit
Instruction Set Summary
MC68HC05E6 — Rev. 1.0
MOTOROLA
Central Processing Unit
103
19-cpu
TST
opr
TSTA
TSTX
TST
opr,X
TST ,X
Test Memory Byte for Negative or Zero
(M) – $00
— — ¤¤ —
DIR
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
4
3
5
4
TXA
Transfer Index Register to Accumulator
A
← (X)
—————
INH
9F
2
WAIT
Stop CPU Clock and Enable Interrupts
0
— — —
INH
8F
2
A Accumulator
opr
Operand (one or two bytes)
C Carry/borrow agPC
Program counter
CCRCondition code registerPCH
Program counter high byte
ddDirect address of operandPCL
Program counter low byte
dd rrDirect address of operand and relative offset of branch instructionREL
Relative addressing mode
DIRDirect addressing mode
rel
Relative program counter offset byte
ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingrr
Relative program counter offset byte
EXTExtended addressing modeSP
Stack pointer
ff Offset byte in indexed, 8-bit offset addressingX
Index register
H Half-carry agZ
Zero ag
hh llHigh and low bytes of operand address in extended addressing#
Immediate value
I Interrupt mask
Logical AND
ii Immediate operand byte
Logical OR
IMMImmediate addressing mode
Logical EXCLUSIVE OR
INHInherent addressing mode( )
Contents of
IXIndexed, no offset addressing mode–( )
Negation (two’s complement)
IX1Indexed, 8-bit offset addressing mode
Loaded with
IX2Indexed, 16-bit offset addressing mode?
If
MMemory location:
Concatenated with
N Negative ag¤
Set or cleared
n Any bit—
Not affected
Table 17 Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
H I NZC
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