參數(shù)資料
型號: MC68HC05E6VDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數(shù): 101/140頁
文件大?。?/td> 1141K
代理商: MC68HC05E6VDWR2
Programmable Timer
Timer state diagrams
MC68HC05E6 — Rev. 1.0
MOTOROLA
Programmable Timer
63
13-ptimer
Figure 14 Timer state timing diagram for output compare
Internal
processor clock
16-bit
counter
$F456
$F457
$F458
$F459
Internal
timer clocks
T00
T01
T11
T10
$F457
CPU writes $F457
Output compare
flag and TCMP
(1) The CPU write to the compare registers may take place at any time, but a compare
only occurs at timer state T01. Thus a four cycle difference may exist between the write
to the compare register and the actual compare.
(2) The output compare flag is set at the timer state T11 that follows the comparison
match ($F457 in this example).
Output compare
register
Compare register
latch
(Note 2)
(Note 1)
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