
MC68F375
CONFIGURABLE TIMER MODULE (CTM9)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
13-39
range from 7.8 milliseconds to 2.0 seconds (assuming a 16.78 MHz MCU clock). By
reducing the counting value, the output signal period can be reduced. The period can
be as fast as 488 microseconds (2.048 KHz) with 12 bits of resolution, as fast as 30.5
microseconds (32.768 KHz) with 8 bits of resolution, and as fast as 7.6 microseconds
(131.072 KHz) with 6 bits of resolution (still assuming a 16.78 MHz system clock and
a first stage prescaler divide-by-2 clock selection). A block diagram of the PWMSM is
Figure 13-13 Pulse Width Modulation Submodule Block Diagram
13.6.1 Output Flip-Flop and Pin
The output flip-flop is the basic output mechanism of the PWMSM. Except when the
required pulse width is 0% or 100%, the output flip-flop is set at the beginning of each
period and is cleared at the end of the designated pulse width. The polarity of the out-
put pulse can be selected in software. The output of the PWMSM is connected to an
external, output-only pin. When the PWMSM is not required, and is disabled by clear-
ing the EN bit in the PWMSIC register, this pin serves as a digital output-only port pin.
When the PWMSM is disabled, the POL bit in the SIC register serves as an output port
bit.
16-bit up counter
IL2
IL1
IL0
IARB3
IL1
State
/ 256 prescaler
CLK1 CLK0
CLK2
Output
Set
Submodule bus
sequencer
buffer
(Ncount)
Zero
detect
Control register bits
PIN
16-bit comparator
Period register
Next period register
PWMA1
PWMA2
Clock
select
16-bit comparator
Pulse width register
Next pulse width
register PWMB1
PWMB2
Output
flip-flop
Interrupt
control
FLAG
POL
LOAD
EN
Clear
All zeros
Match
Load
Enable
PCLK1
Output
pin
PWMC
PWMA
PWMB
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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