
MC68F375
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
5-51
5.12.11 Result Word Table
The result word table is a 64-word long, 10-bit wide RAM. The QADC64 writes a result
word after completing an analog conversion specified by the corresponding CCW. The
result word table can be read or written, but in normal operation, software reads the
result word table to obtain analog conversions from the QADC64. Unimplemented bits
are read as zeros, and write operations have no effect.
While there is only one result word table, the data can be accessed in three different
alignment formats:
Right justified, with zeros in the higher order unused bits.
Left justified, with the most significant bit inverted to form a sign bit, and zeros in
the unused lower order bits.
Left justified, with zeros in the unused lower order bits.
The left justified, signed format corresponds to a half-scale, offset binary, two’s com-
plement data format. The data is routed onto the IMB according to the selected format.
The address used to access the table determines the data alignment format. All write
operations to the result word table are right justified.
The conversion result is unsigned, right justified data. Unused bits return zero when
read.
The conversion result is signed, left justified data. Unused bits return zero when read.
RJURR — Right Justified, Unsigned Result Register
0xYF F680 – 0xYF F6FE
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
RESERVED
RESULT
RESET:
0
LJSRR — Left Justified, Signed Result Register
0xYF F700 – 0xYF F77E
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
S1
NOTES:
1. S = Sign bit.
RESULT
RESERVED
RESET:
0
LJURR — Left Justified, Unsigned Result Register
0xYF F780 – 0xYF F7FE
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
RESULT
RESERVED
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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