
MC68F375
CAN 2.0B CONTROLLER MODULE
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
7-29
7.8.6 Control Register 2
7.8.7 Free Running Timer
Table 7-17 PRESDIV Bit Settings
Bit(s)
Name
Description
15:8
PRESDIV
Prescaler divide factor. PRESDIV determines the ratio between the system clock frequency
and the serial clock (S-clock). The S-clock is determined by the following calculation:
The reset value of PRESDIV is 0x00, which forces the S-clock to default to the same fre-
quency as the system clock. The valid programmed values are 0 through 255.
7:0
CANCTRL2
CANCTRL2 — Control Register 2
0xYF F088
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
PRESDIV
RJW
PSEG
PSEG2
RESET:
0
1
0
Table 7-18 CANCTRL2 Bit Settings
Bit(s)
Name
Description
15:8
PRESDIV
7:6
RJW
Resynchronization jump width. The RJW field defines the maximum number of time quanta
a bit time may be changed during resynchronization. The valid programmed values are 0
through 3.
The resynchronization jump width is calculated as follows:
Resynchronizaton Jump Width = (RJW + 1) Time Quanta
5:3
PSEG1
PSEG1[2:0] — Phase buffer segment 1. The PSEG1 field defines the length of phase buffer
segment 1 in the bit time. The valid programmed values are 0 through 7.
The length of phase buffer segment 1 is calculated as follows:
Phase Buffer Segment 1 = (PSEG1 + 1) Time Quanta
2:0
PSEG2
PSEG2 — Phase Buffer Segment 2. The PSEG2 field defines the length of phase buffer seg-
ment 2 in the bit time. The valid programmed values are 0 through 7.
The length of phase buffer segment 2 is calculated as follows:
Phase Buffer Segment 2 = (PSEG2 + 1) Time Quanta
TIMER — Free Running Timer Register
0xYF F08A
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
TIMER
RESET:
0
1
0
S-clock
f
sys
PRESDIV
1
+
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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