
MC68F375
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
5-38
5.12.6 QADC64 Control Register 1 (QACR1)
Control register 1 is the mode control register for the operation of queue 1. The appli-
cations software defines the queue operating mode for the queue, and may enable a
completion and/or pause interrupt. All of the control register fields are read/write data.
However, the SSE1 bit always reads as zero unless the test mode is enabled. Most of
the bits are typically written once when the software initializes the QADC64, and not
changed afterwards.
Table 5-11 QACR0 Bit Settings
Bit(s)
Name
Description
15
MUX
Externally multiplexed mode. The MUX bit configures the QADC64 for externally multiplexed
mode, which affects the interpretation of the channel numbers and forces the MA[2:0] pins to be
outputs.
0 = Internally multiplexed, 16 possible channels. AMUX is disabled.
1 = Externally multiplexed, 41 possible channels. This enables the on-chip AMUX.
14:13
—
Reserved
12
TRG
Trigger assignment. TRG allows the software to assign the ETRIG[2:1] pins to queue 1 and
queue 2.
0 = ETRIG1 triggers queue 1; ETRIG2 triggers queue 2
1 = ETRIG1 triggers queue 2; ETRIG2 triggers queue 1
11:9
—
Reserved
8:4
PSH
Prescaler clock high time. The PSH field selects the QCLK high time in the prescaler. PSH value
plus 1 represents the high time in system clocks
3
PSA
Note that this bit location is maintained for software compatibility with previous versions of the
QADC64. It serves no functional benefit in the MC68F375 and is not operational.
2:0
PSL
Prescaler clock low time. The PSL field selects the QCLK low time in the prescaler. PSL value
plus 1 represents the low time in system clocks
QACR1 — Control Register 1
0xYF F40C
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
CIE1
PIE1
SSE1
MQ1
RESERVED
RESET:
0
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Freescale Semiconductor, Inc.
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