Applications
MOTOROLA
MC68360 USER’S MANUAL
9-3
9.1.1.2 CLOCKING STRATEGY.
32.768-kHz crystal into the QUICC. The QUICC's internal phase-locked loop (PLL) then
multiplies the frequency up to 25 MHz, and outputs 25 MHz on CLKO1 and 50 MHz on
CLKO2. Neither CLKO pin is required for the application. It is recommended that the CLKO
outputs be disabled in software to save power.
In this application, the system clock is generated from a
The use of a 32.768-kHz crystal is not a requirement in the application. A 4-MHz crystal or
a 25-MHz external oscillator could have been used, if desired.
The QUICC clocking section allows for the clock oscillator to be kept running through the
VDDSYN pin in a power-down situation. This section does not address low-power issues,
however.
9.1.1.3 RESETTING THE QUICC.
select, it will also provide an internal power-on reset generation. Thus, the reset support
function is very simple. If a pushbutton switch is needed, it can be connected by an open-
drain buffer to the hard reset (RESETH) pin, once debounced. The soft reset (RESETS) pin
is not used in this design except to indicate that an internal QUICC soft reset is in progress.
If a QUICC is configured to provide the global chip
9.1.1.4 INTERRUPTS.
the IRQx pins or parallel I/O pins. This design shows no external interrupts (the IRQ7–IRQ1
pins are pulled high), but this could be easily changed if desired. Without any external inter-
rupts requiring autovector capability, the AVEC pin is also pulled high.
External interrupts may be brought into the QUICC through either
Internal interrupts from the QUICC may be generated in the SIM60 or the CPM. No addi-
tional hardware is required.
9.1.1.5 BUS ARBITRATION.
the system. Thus, BR is pulled high, and BGACK is not connected, but pulled high since it
is an open-drain signal.
This design assumes that no alternate bus masters exist in
9.1.1.6 BREAKPOINT GENERATION.
breakpoint signal. The result of a breakpoint (either internally generated using the break-
point address register or externally generated using the BKPT pin) is a CPU32+ breakpoint
cycle. In this application, the BKPT pin is tied high and is not used.
The QUICC can be used to generate a hardware
9.1.1.7 BUS MONITOR FUNCTION.
bus cycles that are not properly terminated. If AS is asserted but not negated, the cycle will
terminate with the BERR pin being asserted.
The QUICC can be programmed to monitor the bus for
9.1.1.8 SPURIOUS INTERRUPT MONITOR.
cycles on the levels that it supports internally. If such a condition occurs, BERR will be
asserted by the QUICC.
The QUICC will watch for spurious interrupt
9.1.1.9 SOFTWARE WATCHDOG.
to generate a level 7 interrupt or a system reset. In this application, the software watchdog
is configured in software to generate a reset. No additional hardware is required.
If desired, the QUICC software watchdog can be used