Bus Operation
MOTOROLA
MC68360 USER’S MANUAL
4-53
4.6.2 Bus Grant
The QUICC supports operand coherency; thus, if an operand transfer requires multiple bus
cycles, the QUICC does not release the bus until the entire transfer is complete. The asser-
tion of BG is therefore subject to the following constraints:
The minimum time for BG assertion after BR is asserted depends on internal synchro-
nization.
When working in synchronous mode (ASTM bit in the MCR is set), the minimum time
can be one clock.
During an external operand transfer, the QUICC does not assert BG until after the last
cycle of the transfer (determined by SIZx and DSACKx).
During an external operand transfer, the QUICC does not assert BG as long as RMC is
asserted.
If the show cycle bits SHEN1–SHEN0 = 1x and if one of the QUICC internal masters is
making internal accesses, the QUICC does not assert BG until the transfer is terminat-
ed.
If SHEN1–SHEN0 = 00 and if one of the QUICC internal masters is making internal ac-
cesses, the external bus is granted away, and the QUICC continues to execute internal
bus cycles. In this case, the arbitration overhead (external bus idle time) is minimal.
If SHEN1–SHEN0 = 01, the QUICC does not assert BG to an external master.
Externally, the BG signal can be routed through a daisy-chained network or a priority-
encoded network. The QUICC is not affected by the method of arbitration as long as the pro-
tocol is obeyed.
4.6.3 Bus Grant Acknowledge
An external device cannot request and be granted the external bus while another device is
the active bus master. A device that asserts BGACK remains the bus master until it negates
BGACK. BGACK should not be negated until all required bus cycles are completed. Bus
mastership is terminated at the negation of BGACK. When no other device requests the bus
after BGACK is negated, the QUICC will regain bus mastership.
The minimum time for the first bus cycle after BGACK negation depends on internal syn-
chronization and internal bus arbitration. This timing is therefore subject to the following con-
straints:
When working in synchronous mode (ASTM bit in the MCR is set) and SHEN0–SHEN1
= 00 and one of the QUICC internal masters requests an external accesses, the mini-
mum time can be one clock.
When working in asynchronous mode (ASTM bit in the MCR is cleared) and SHEN0–1
= 00 and one of the QUICC internal masters requests an external accesses, the mini-
mum time depends on internal synchronization plus one clock.
If SHEN1–SHEN0 = 1
×
, another clock is added for internal bus arbitration.