參數(shù)資料
型號(hào): MC68CK338
廠商: Motorola, Inc.
元件分類: 32位微控制器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 高度集成,低功耗,32位微控制器
文件頁(yè)數(shù): 59/133頁(yè)
文件大?。?/td> 798K
代理商: MC68CK338
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MC68CK338
MC68CK338TS/D
MOTOROLA
59
5.3 Pin Function
Table 36
is a summary of the functions of the QSM pins when they are not configured for general-pur-
pose I/O. The QSM data direction register (DDRQS) designates each pin except RXD as an input or
output.
5.4 QSM Registers
QSM registers are divided into four categories: QSM global registers, QSM pin control registers, QSPI
submodule registers, and SCI submodule registers. The QSPI and SCI registers are defined in separate
sections below. Writes to unimplemented register bits have no meaning or effect, and reads from unim-
plemented bits always return a logic zero value.
The module mapping bit of the SIML configuration register (SIMLCR) defines the most significant bit
(ADDR23) of the address, shown in each register figure as Y (Y = $7 or $F). This bit, concatenated with
the rest of the address given, forms the absolute address of each register. Refer to the SIML section of
this technical summary for more information about how the state of MM affects the system.
5.4.1 Global Registers
The QSM global registers contain system parameters used by both the QSPI and the SCI submodules.
These registers contain the bits and fields used to configure the QSM.
The QSMCR contains parameters for the QSM/CPU/intermodule bus (IMB) interface.
Table 36 QSM Pin Functions
Pin
MISO
Mode
Master
Slave
Master
Slave
Master
Slave
Pin Function
Serial data input to QSPI
Serial data output from QSPI
Serial data output from QSPI
Serial data input to QSPI
Clock output from QSPI
Clock input to QSPI
Input: Assertion causes mode fault
Output: Selects peripherals
Input: Selects the QSPI
Output: Selects peripherals
None
Serial data output from SCI
Serial data input to SCI
QSPI Pins
MOSI
SCK
PCS0/SS
Master
Slave
Master
Slave
Transmit
Receive
PCS[3:1]
SCI Pins
TXD
RXD
QSMCR —
QSM Configuration Register
$YFFC00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOP
FRZ1
FRZ0
0
0
0
0
0
SUPV
0
0
0
IARB
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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