參數(shù)資料
型號: MC68CK338
廠商: Motorola, Inc.
元件分類: 32位微控制器
英文描述: Highly Integrated, Low-Power, 32-Bit Microcontroller
中文描述: 高度集成,低功耗,32位微控制器
文件頁數(shù): 129/133頁
文件大?。?/td> 798K
代理商: MC68CK338
MC68CK338
MC68CK338TS/D
MOTOROLA
129
Figure 39 Background Debugging Mode Timing Diagram —
Freeze Assertion
NOTES:
1. All AC timing is shown with respect to 20% V
DD
and 70% V
DD
levels unless otherwise noted.
2. When the previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t
Ecyc
– t
EAD
– t
EDSR
.
4. Chip select access time = t
Ecyc
– t
ECSD
– t
EDSR
.
Table 73 ECLK Bus Timing
(V
DD
and V
DDSYN
= 2.7 to 3.6 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
)
1
Num
Characteristic
Symbol
Min
Max
Unit
1A
ECLK Period
t
Ecyc
555
ns
2A, 3A
ECLK Pulse Width
t
ECW
277.5
ns
E1
ECLK Low to Address Valid
2
t
EAD
70
ns
E2
ECLK Low to Address Hold
t
EAH
10
ns
E3
ECLK Low to CS Valid (CS delay)
t
ECSD
140
ns
E4
ECLK Low to CS Hold
t
ECSH
10
ns
E5
CS Negated Width
t
ECSN
35
ns
E6
Read Data Setup Time
t
EDSR
35
ns
E7
Read Data Hold Time
t
EDHR
5
ns
E8
ECLK Low to Data High Impedance
t
EDHZ
130
ns
E9
CS Negated to Data Hold (Read)
t
ECDH
0
ns
E10
CS Negated to Data High Impedance
t
ECDZ
1
t
cyc
E11
ECLK Low to Data Valid (Write)
t
EDDW
2
t
cyc
E12
ECLK Low to Data Hold (Write)
t
EDHW
10
ns
E13
Address Access Time (Read)
3
t
EACC
450
ns
E14
Chip Select Access Time (Read)
4
t
EACS
380
ns
E15
Address Setup Time
t
EAS
1/2
t
cyc
68300 BDM FRZ TIM
B8
CLKOUT
FREEZE
IFETCH/DSI
B6
B6
B7
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