- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371046 > MC68CK338 (Motorola, Inc.) Highly Integrated, Low-Power, 32-Bit Microcontroller PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68CK338 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁(yè)數(shù)： | 24/133頁(yè) |
| 文件大?。?/td> | 798K |
| 代理商： | MC68CK338 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)當(dāng)前第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)
MOTOROLA
24
MC68CK338
MC68CK338TS/D
The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cy-
cle. The BME bit in SYPCR enables the internal bus monitor for internal to external bus cycles. If a sys-
tem contains external bus masters, an external bus monitor must be implemented and the internal to
external bus monitor option must be disabled.
3.4.3 Halt Monitor
The halt monitor responds to assertion of the HALT signal on the internal bus caused by a double bus
fault. A double bus fault occurs when:
Bus error exception processing begins and a second BERR is detected before the first instruction
of the first exception handler is executed.
One or more bus errors occur before the first instruction after a reset exception is executed.
A bus error occurs while the CPU is loading information from a bus error stack frame during a re-
turn from exception (RTE) instruction.
If the halt monitor is enabled by setting HME in SYPCR, the MCU will issue a reset when a double bus
fault occurs, otherwise the MCU will remain halted.
A flag in the reset status register (RSR) indicates that the last reset was caused by the halt monitor.
3.4.4 Spurious Interrupt Monitor
The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an interrupt ac-
knowledge cycle. Leaving IARB[3:0] set to %0000 in the module configuration register of any peripheral
that can generate interrupts will cause a spurious interrupt.
3.4.5 Software Watchdog
The software watchdog is controlled by SWE in SYPCR. Once enabled, the watchdog requires that a
service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watchdog
times out and issues a reset. This register can be written at any time, but returns zeros when read.
Each time the service sequence is written, the software watchdog timer restarts. The servicing se-
quence consists of the following steps:
1.
2.
Write $55 to SWSR.
Write $AA to SWSR.
Both writes must occur before time-out in the order listed, but any number of instructions can be exe-
cuted between the two writes.
The watchdog clock rate is affected by SWP and SWT[1:0] in SYPCR. When SWT[1:0] are modified, a
watchdog service sequence must be performed before the new time-out period takes effect.
The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of RESET. Refer
to
Table 11
.
SWSR —
Software Service Register
$YFFA27
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
SWSR
RESET:
0
0
0
0
0
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68EC060 | 32-Bit Microprocessors.(32位微處理器) |
| MC68EN360RC25V | QUad Integrated Communications Controller Users Manual |
| MC68EN360CFE25 | QUad Integrated Communications Controller Users Manual |
| MC68EN360FE25 | AC 4C 4#12 PIN PLUG 023 |
| MC68EN360FE25V | QUad Integrated Communications Controller Users Manual |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68CK338CPV14 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68CK338CPV14B1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68CM16Z1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
| MC68CM16Z1CFC16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
| MC68CM16Z1CPV16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。