MOTOROLA
M68040 USER’S MANUAL
xvii
LIST OF ILLUSTRATIONS
Figure
Page
Number
Title
Number
1-1
Block Diagram ..............................................................................................1-4
1-2
Programming Model .....................................................................................1-7
2-1
Integer Unit Pipeline ..................................................................................... 2-2
2-2
Write-Back Cycle Block Diagram ................................................................. 2-3
2-3
Integer Unit User Programming Model......................................................... 2-4
2-4
Integer Unit Supervisor Programming Model ............................................... 2-6
2-5
Status Register............................................................................................. 2-7
3-1
Memory Management Unit ........................................................................... 3-2
3-2
Memory Management Programming Model ................................................. 3-3
3-3
URP and SRP Register Formats.................................................................. 3-4
3-4
Translation Control Register Format ............................................................ 3-4
3-5
Transparent Translation Register Format ....................................................3-5
3-6
MMU Status Register Format....................................................................... 3-6
3-7
Translation Table Structure .......................................................................... 3-8
3-8
Logical Address Format ...............................................................................3-9
3-9
Detailed Flowchart of Table Search Operation ............................................ 3-10
3-10
Detailed Flowchart of Descriptor Fetch Operation ....................................... 3-11
3-11
Table Descriptor Formats............................................................................. 3-13
3-12
Page Descriptor Formats ............................................................................. 3-13
3-13
Example Translation Table .......................................................................... 3-17
3-14
Translation Table Using Indirect Descriptors ............................................... 3-18
3-15
Translation Table Using Shared Tables ....................................................... 3-19
3-16
Translation Table with Nonresident Tables .................................................. 3-20
3-17
Translation Table Structure for Two Tasks .................................................. 3-24
3-18
Logical Address Map with Shared Supervisor and User Address Spaces... 3-24
3-19
Translation Table Using S-Bit and W-Bit To Set Protection ......................... 3-25
3-20
ATC Organization......................................................................................... 3-26
3-21
ATC Entry and Tag Fields ............................................................................ 3-27
3-22
Address Translation Flowchart..................................................................... 3-32
3-23
MMU Status Interpretation ........................................................................... 3-35
4-1
Overview of Internal Caches ........................................................................ 4-2
4-2
Cache Line Formats ..................................................................................... 4-3
4-3
Caching Operation ....................................................................................... 4-4
4-4
Cache Control Register ................................................................................ 4-5
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Freescale Semiconductor, Inc.
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