參數(shù)資料
型號： MC56F8346VFVER2
廠商： Freescale Semiconductor
文件頁數(shù)： 98/178頁
文件大小： 0K
描述： IC HYBRID CTRLR 16BIT 144-LQFP
標準包裝： 500
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 60MHz
連通性： CAN，EBI/EMI，SCI，SPI
外圍設備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 62
程序存儲器容量： 136KB（68K x 16）
程序存儲器類型： 閃存
RAM 容量： 6K x 16
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 144-LQFP
包裝： 帶卷 (TR)
配用： MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8346 Technical Data, Rev. 15
26
Freescale Semiconductor
Preliminary
RD
45
Output
In reset,
output is
disabled,
pull-up is
enabled
Read Enable — RD is asserted during external memory read
cycles. When RD is asserted low, pins D0 - D15 become inputs
and an external device is enabled onto the data bus. When RD is
deasserted high, the external data is latched inside the device.
When RD is asserted, it qualifies the A0 - A16, PS, DS, and CSn
pins. RD can be connected directly to the OE pin of a static RAM or
ROM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), RD is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in the
SIM_PUDR register.
WR
44
Output
In reset,
output is
disabled,
pull-up is
enabled
Write Enable — WR is asserted during external memory write
cycles. When WR is asserted low, pins D0 - D15 become outputs
and the device puts data on the bus. When WR is deasserted high,
the external data is latched inside the external device. When WR is
asserted, it qualifies the A0 - A16, PS, DS, and CSn pins. WR can
be connected directly to the WE pin of a static RAM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), WR is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in the
SIM_PUDR register.
PS
(CS0)
(GPIOD8)
46
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Program Memory Select — This signal is actually CS0 in the EMI,
which is programmed at reset for compatibility with the 56F80x PS
signal. PS is asserted low for external program memory access.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), PS is tri-stated when the external bus is inactive.
CS0 resets to provide the PS function as defined on the 56F80x
devices.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.
Table 2-2 Signal and Package Information for the 144 Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
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