參數資料
型號: MC56F8346VFVER2
廠商: Freescale Semiconductor
文件頁數: 23/178頁
文件大?。?/td> 0K
描述: IC HYBRID CTRLR 16BIT 144-LQFP
標準包裝: 500
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設備: POR,PWM,溫度傳感器,WDT
輸入/輸出數: 62
程序存儲器容量: 136KB(68K x 16)
程序存儲器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數據轉換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LQFP
包裝: 帶卷 (TR)
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
Register Descriptions
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
119
Preliminary
6.5.8
GPIO Peripheral Select Register (SIM_GPS)
The GPIO Peripheral Select register can be used to multiplex out any one of the three alternate peripherals
for GPIOC. The default peripheral is Quad Decoder 1 and Quad Timer B (NOT available in the 56F8146
device); these peripherals work together.
The four I/O pins associated with GPIOC can function as GPIO, Quad Decoder 1/Quad Timer B, or as
SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown in
Figure 6-10 and Table 6-2. When GPIOC[3:0] are programmed to operate as peripheral I/O, then the
choice between decoder/timer and SPI inputs/outputs is made in the SIM_GPS register and in conjunction
with the Quad Timer Status and Control Registers (SCR). The default state is for the peripheral function
of GPIOC[3:0] to be programmed as decoder functions. This can be changed by altering the appropriate
controls in the indicated registers.
Figure 6-10 Overall Control of Pads Using SIM_GPS Control
GPIOC_PER Register
GPIO Controlled
I/O Pad Control
SIM_ GPS Register
Quad Timer Controlled
SPI Controlled
0
1
0
1
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