參數(shù)資料
型號： MC56F8346VFVER2
廠商： Freescale Semiconductor
文件頁數(shù)： 54/178頁
文件大?。?/td> 0K
描述： IC HYBRID CTRLR 16BIT 144-LQFP
標準包裝： 500
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 60MHz
連通性： CAN，EBI/EMI，SCI，SPI
外圍設備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 62
程序存儲器容量： 136KB（68K x 16）
程序存儲器類型： 閃存
RAM 容量： 6K x 16
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 144-LQFP
包裝： 帶卷 (TR)
配用： MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
Crystal Oscillator Timing
56F8346 Technical Data, Rev. 15
Freescale Semiconductor
147
Preliminary
10.7 Crystal Oscillator Timing
10.8 External Memory Interface Timing
The External Memory Interface is designed to access static memory and peripheral devices. Figure 10-4
shows sample timing and parameters that are detailed in Table 10-16.
The timing of each parameter consists of both a fixed delay portion and a clock related portion, as well as
user controlled wait states. The equation:
t = D + P * (M + W)
should be used to determine the actual time of each parameter. The terms in this equation are defined as:
When using the XTAL clock input directly as the chip clock without prescaling (ZSRC selects prescaler
clock and prescaler is set to ÷ 1), the EMI quadrature clock is generated using both edges of the EXTAL
clock input. In this situation only, parameter values must be adjusted for the duty cycle at XTAL. DCAOE
3. This is the minimum time required after the PLL set up is changed to ensure reliable operation.
Table 10-15 Crystal Oscillator Parameters
Characteristic
Symbol
Min
Typ
Max
Unit
Crystal Start-up time
TCS
45
10
ms
Resonator Start-up time
TRS
0.1
0.18
1
ms
Crystal ESR
RESR
——
120
ohms
Crystal Peak-to-Peak Jitter
TD
70
—
250
ps
Crystal Min-Max Period Variation
TPV
0.12
—
1.5
ns
Resonator Peak-to-Peak Jitter
TRJ
——
300
ps
Resonator Min-Max Period Variation
TRP
——
300
ps
Bias Current, high-drive mode
IBIASH
—250
290
μA
Bias Current, low-drive mode
IBIASL
—80
110
μA
Quiescent Current, power-down mode
IPD
—0
1
μA
t
= Parameter delay time
D
= Fixed portion of the delay, due to on-chip path delays
P
= Period of the system clock, which determines the execution rate of the part
(i.e., when the device is operating at 60MHz, P = 16.67 ns)
M
= Fixed portion of a clock period inherent in the design; this number is adjusted to account
for possible derating of clock duty cycle
W
= Sum of the applicable wait state controls. The “Wait State Controls” column of
Table 10-16 shows the applicable controls for each parameter and the EMI chapter of the
56F8300 Peripheral User Manual details what each wait state field controls.
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