參數(shù)資料
型號: MC56F8346VFVER2
廠商: Freescale Semiconductor
文件頁數(shù): 109/178頁
文件大?。?/td> 0K
描述: IC HYBRID CTRLR 16BIT 144-LQFP
標準包裝: 500
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 62
程序存儲器容量: 136KB(68K x 16)
程序存儲器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LQFP
包裝: 帶卷 (TR)
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8346 Technical Data, Rev. 15
36
Freescale Semiconductor
Preliminary
ISB0
(GPIOD10)
50
Schmitt
Input
Schmitt
Input/
Output
Input,
pull-up
enabled
ISB0 - 2 — These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMB.
Port D GPIO — These three GPIO pins can be individually
programmed as input or output pins.
At reset, these pins default to ISB functionality.
To deactivate the internal pull-up resistor, clear the appropriate bit
of the GPIOD_PUR register. For details, see Part 6.5.8.
ISB1
(GPIOD11)
52
ISB2
(GPIOD12)
53
FAULTB0
56
Schmitt
Input
Input,
pull-up
enabled
FAULTB0 - 3 — These four fault input pins are used for disabling
selected PWMB outputs in cases where fault conditions originate
off-chip.
To deactivate the internal pull-up resistor, set the PWMB bit in the
SIM_PUDR register. For details, see Part 6.5.8.
FAULTB1
57
FAULTB2
58
FAULTB3
61
ANA0
88
Input
Analog
Input
ANA0 - 3 — Analog inputs to ADC A, channel 0
ANA1
89
ANA2
90
ANA3
91
ANA4
92
Input
Analog
Input
ANA4 - 7 — Analog inputs to ADC A, channel 1
ANA5
93
ANA6
94
ANA7
95
VREFH
101
Input
Analog
Input
VREFH — Analog Reference Voltage High. VREFH must be less
than or equal to VDDA_ADC.
VREFP
100
Input/
Output
Analog
Input/
Output
VREFP, VREFMID & VREFN — Internal pins for voltage reference
which are brought off-chip so they can be bypassed. Connect to a
0.1
μF low ESR capacitor.
VREFMID
99
VREFN
98
VREFLO
97
Input
Analog
Input
VREFLO — Analog Reference Voltage Low. This should normally
be connected to a low-noise VSSA.
Table 2-2 Signal and Package Information for the 144 Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
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