LOGIC COMMANDS AND REGISTERS Table 8. List " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MC33889DEG
寤�(ch菐ng)鍟嗭細 Freescale Semiconductor
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 37/59闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC SYSTEM BASE W/CAN 28-SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
鎺у埗鍣ㄩ(l猫i)鍨嬶細 绯荤当(t菕ng)鍩虹(ch菙)鑺墖
鎺ュ彛锛� CAN
闆绘簮闆诲锛� 5.5 V ~ 18 V
闆绘祦 - 闆绘簮锛� 45mA
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
灏佽/澶栨锛� 28-SOIC锛�0.295"锛�7.50mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 28-SOIC W
鍖呰锛� 绠′欢
Analog Integrated Circuit Device Data
42
Freescale Semiconductor
33889
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 8. List of Registers
NOTE: For SPI Operation
In case a low pulse is asserted by the device on the RST output pin during a SPI message,
the SPI message can be corrupted. An RST low pulse is asserted in 2 cases:
Case 1: W/D refresh issue: The MCU does not perform the SPI watchdog refresh command
before the expiration of the timeout (in Normal mode or Normal Request mode and if the
鈥淭imeout watchdog鈥� option is selected), or the SPI watchdog refresh command is performed
in the closed window (in Normal mode and if 鈥淲indow watchdog鈥� option is selected).
Case 2: VDD undervoltage condition: VDD falls below the VDD undervoltage threshold.
Message corruption means that the targeted register address can be changed, and another
register is written. Table 9 shows the various cases and impacts on SPI register address:
Name
Address
Description
Comment and usage
MCR
$0 0 0
Mode control register
Write: Control of normal, standby, sleep, and stop modes
Read: BATFAIL flag and other status bits and flags
RCR
$0 0 1
Reset control register
Write: Configuration of reset voltage level, WD in stop mode, low power
mode selection
Read: CAN wake-up event, Tx permanent dominant
CAN
$0 1 0
CAN control register
Write: CAN module control: TX/RX, Rec only, term VBAT, Normal and
extended modes, filter at L0 input.
Read: CAN failure status bits
IOR
$0 1 1
I/O control register
Write: HS1 (high-side switch) control in normal and standby mode.
Gnd shift register level selection
Read: HS1 over temp bit, SHIFT bit (gnd shift above selection), VSUP
below 6.1V, V2 below 4.0 V
WUR
$1 0 0
Wake-up input register
Write: Control of wake-up input polarity
Read: Wake-up input, and real time LX input state
TIM
$1 0 1
Timing register
Write: TIM1, Watchdog timing control, window or Timeout mode.
Write: TIM2, Cyclic sense and force wake-up timing selection
LPC
$1 1 0
Low power mode
control register
Write: HS1 periodic activation in sleep and stop modes
Force wake-up control
INTR
$1 1 1
Interrupt register
Write: Interrupt source configuration
Read: INT source
Table 9. Possible Corrupted Registers In Case of RST Pulse During SPI Communication
Resulting Written register
Register
MCR
RCR
CAN
IOR
Address
$000
$001
$010
$011
Target
written
register
Register
Address
CAN
$010
X
IOR
$011
X
WUR
$100
X
TIM1/2
$101
X
LPC
$110
X
INTR
$111
X
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