- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗11545 > MC33889DEG (Freescale Semiconductor)IC SYSTEM BASE W/CAN 28-SOIC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | MC33889DEG |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 21/59闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC SYSTEM BASE W/CAN 28-SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 24 |
| 鎺у埗鍣ㄩ鍨嬶細 | 绯荤当(t菕ng)鍩虹(ch菙)鑺墖 |
| 鎺ュ彛锛� | CAN |
| 闆绘簮闆诲锛� | 5.5 V ~ 18 V |
| 闆绘祦 - 闆绘簮锛� | 45mA |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 28-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 28-SOIC W |
| 鍖呰锛� | 绠′欢 |
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Analog Integrated Circuit Device Data
28
Freescale Semiconductor
33889
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SOFTWARE WATCHDOG IN STOP MODE
If the watchdog is enabled (register MCR, bit WDSTOP set), the MCU has to wake-up independently of the SBC before the
end of the SBC watchdog time. In order to do this, the MCU has to signal the wake-up to the SBC through the SPI wake-up (CS
pin low to high transition to activated the SPI wake-up). Then the SBC wakes up and jumps into the normal request mode. The
MCU has to configure the SBC to go to either into normal or standby mode. The MCU can then choose to go back into stop mode.
If no MCU wake-up occurs within the watchdog timing, the SBC will activate the reset pin and jump into the normal request
mode. The MCU can then be initialized.
NORMAL REQUEST MODE
This is a temporary mode automatically accessed by the device after a wake-up event from sleep or stop mode, or after device
power up. In this mode, the VDD1 regulator is ON, V2 is off, and the reset pin is high. As soon as the device enters the normal
request mode, an internal 350 ms timer is started. During these 350 ms, the microcontroller of the application must address the
SBC via the SPI and configure the watchdog register (TIM1 register). This is the condition for the SBC to leave the Normal request
Mode and enter the Normal mode, and to set the watchdog timer according to the configuration done during the Normal Request
mode.
The 鈥淏ATFAIL flag鈥� is a bit which is triggered when VSUP falls below 3.0 V. This bit is set into the MCR register. It is reset by
the MCR register read.
INTERNAL CLOCK
This device has an internal clock used to generate all timings (reset, watchdog, cyclic wake-up, filtering time etc...).
RESET PIN
A reset output is available in order to reset the microcontroller. Reset causes are:
VDD1 falling out of range: if VDD1 falls below the reset threshold (parameter RST-TH), the reset pin is pulled low until VDD1 returns
to the nominal voltage.
Power on reset: at device power on or at device wake-up from sleep mode, the reset is maintained low until VDD1 is within its
operation range.
Watchdog timeout: if the watchdog is not cleared, the SBC will pull the reset pin low for the duration of the reset duration time
(parameter: RESET-DUR).
For debug purposes at 25 掳C, the reset pin can be shorted to 5.0 V.
SOFTWARE WATCHDOG (SELECTABLE WINDOW OR TIMEOUT WATCHDOG)
The software watchdog is used in the SBC normal and stand-by modes for monitoring the MCU. The watchdog can be either
a window or timeout. This is selectable by the SPI (register TIM, bit WDW). Default is the window watchdog. The period of the
watchdog is selectable by the SPI from 5.0 to 350 ms (register TIM, bits WDT0 and WDT1). When the window watchdog is
selected, the closed window is the first half of the selected period, and the open window is the second half of the period. The
watchdog can only be cleared within the open window time. An attempt to clear the watchdog in the closed window will generate
a reset. The Watchdog is cleared through the SPI by addressing the TIM register.
Refer to 鈥漷able for reset pin operations鈥� operation in mode 2.
WAKE-UP CAPABILITIES
Several wake-up capabilities are available for the device when it is in sleep or stop mode. When a wake-up has occurred, the
wake-up event is stored into the WUR or CAN registers. The MCU can then access the wake-up source. The wake-up options
are selectable through the SPI while the device is in normal or standby mode, and prior to entering low power mode (Sleep or
Stop mode).
WAKE-UP FROM WAKE-UP INPUTS (L0, L1) WITHOUT CYCLIC SENSE
The wake-up lines are dedicated to sense external switch states, and when changes occur to wake-up the MCU (In sleep or
stop modes). The wake-up pins are able to handle 40 V DC. The internal threshold is 3.0 V typical, and these inputs can be used
as an input port expander. The wake-up inputs state can be read through the SPI (register WUR). L0 has a lower threshold than
L1 in order to allow a connection and wake-up from a digital output such as a CAN physical interface.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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| MC33889DW | 鍔熻兘鎻忚堪:IC SYSTEM BASE W/CAN 28-SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 鎺у埗鍣� 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:4,900 绯诲垪:- 鎺у埗鍣ㄩ鍨�:USB 2.0 鎺у埗鍣� 鎺ュ彛:涓茶 闆绘簮闆诲:3 V ~ 3.6 V 闆绘祦 - 闆绘簮:135mA 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:36-VFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:36-QFN锛�6x6锛� 鍖呰:* 鍏跺畠鍚嶇ū:Q6396337A |
| MC33889DWR2 | 鍔熻兘鎻忚堪:IC SYSTEM BASE W/CAN 28-SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 鎺у埗鍣� 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:4,900 绯诲垪:- 鎺у埗鍣ㄩ鍨�:USB 2.0 鎺у埗鍣� 鎺ュ彛:涓茶 闆绘簮闆诲:3 V ~ 3.6 V 闆绘祦 - 闆绘簮:135mA 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:36-VFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:36-QFN锛�6x6锛� 鍖呰:* 鍏跺畠鍚嶇ū:Q6396337A |
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