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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MC33889DEG |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 24/59闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC SYSTEM BASE W/CAN 28-SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 24 |
| 鎺у埗鍣ㄩ鍨嬶細 | 绯荤当(t菕ng)鍩虹(ch菙)鑺墖 |
| 鎺ュ彛锛� | CAN |
| 闆绘簮闆诲锛� | 5.5 V ~ 18 V |
| 闆绘祦 - 闆绘簮锛� | 45mA |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 28-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 28-SOIC W |
| 鍖呰锛� | 绠′欢 |
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Analog Integrated Circuit Device Data
30
Freescale Semiconductor
33889
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 11. Reset and WDOG Function Diagram
DEBUG MODE APPLICATION HARDWARE AND SOFTWARE DEBUG WITH THE SBC.
When the SBC is mounted on the same printed circuit board as the micro controller, it supplies both application software and
the SBC with a dedicated routine that must be debugged. The following features allow the user to debug the software by disabling
the SBC internal software watchdog timer.
DEVICE POWER UP, RESET PIN CONNECTED TO VDD1
At SBC power up, the VDD1 voltage is provided, but if no SPI communication occurs to configure the device, a reset occurs
every 350 ms. In order to allow software debugging and avoid an MCU reset, the Reset pin can be connected directly to VDD1
by a jumper.
DEBUG MODES WITH SOFTWARE WATCHDOG DISABLED THOUGH SPI (NORMAL DEBUG, STANDBY DEBUG AND
STOP DEBUG)
The software watchdog can be disabled through the SPI. In order to avoid unwanted watchdog disables, and to limit the risk
of disabling the watchdog during an SBC normal operation, the watchdog disable has to be performed with the following
sequence:
Step 1) Power down the SBC
Step 2) Power up the SBC (The BATFAIL bit is set, and the SBC enters normal request mode)
Step 3) Write to the TIM1 register to allow the SBC to enter Normal mode
Step 4) Write to the MCR register with data 0000 (this enables the debug mode). (Complete SPI byte: 000 1 0000)
Step 5) Write to the MCR register normal debug (0001 x101), stand-by debug (0001 x110), or Stop debug (0001 x111)
While in debug mode, the SBC can be used without having to clear the W/D on a regular basis to facilitate software and
hardware debugging.
Step 6) To leave the debug mode, write 0000 to the MCR register.
To avoid entering the debug mode after a power up, first read the BATFAIL bit (MCR read) and write 0000 into the MCR.
Figure 12 illustrates entering the debug mode.
RESET
WDOG
VDD1
SPI
SPI CS
Watchdog timeout
Watchdog register addressed
Watchdog
period
W/D clear
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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| VE-22V-IX-S | CONVERTER MOD DC/DC 5.8V 75W |
| V72A12C400B3 | CONVERTER MOD DC/DC 12V 400W |
| VI-23B-IX-S | CONVERTER MOD DC/DC 95V 75W |
| V48C5M75BL3 | CONVERTER MOD DC/DC 5V 75W |
| V48C5M75BG2 | CONVERTER MOD DC/DC 5V 75W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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| MC33889DPEG | 鍔熻兘鎻忚堪:CAN 鎺ュ彛闆嗘垚闆昏矾 SBC-LITE-LS-CAN RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷:Transceivers 宸ヤ綔闆绘簮闆诲:5 V 闆绘簮闆绘祦: 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 灏佽 / 绠遍珨:SOIC-8 灏佽:Tube |
| MC33889DPEGR2 | 鍔熻兘鎻忚堪:CAN 鎺ュ彛闆嗘垚闆昏矾 SBC-LITE-LS-CAN RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷:Transceivers 宸ヤ綔闆绘簮闆诲:5 V 闆绘簮闆绘祦: 宸ヤ綔婧害鑼冨湇:- 40 C to + 85 C 灏佽 / 绠遍珨:SOIC-8 灏佽:Tube |
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| MC33889DWR2 | 鍔熻兘鎻忚堪:IC SYSTEM BASE W/CAN 28-SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 鎺у埗鍣� 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:4,900 绯诲垪:- 鎺у埗鍣ㄩ鍨�:USB 2.0 鎺у埗鍣� 鎺ュ彛:涓茶 闆绘簮闆诲:3 V ~ 3.6 V 闆绘祦 - 闆绘簮:135mA 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:36-VFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:36-QFN锛�6x6锛� 鍖呰:* 鍏跺畠鍚嶇ū:Q6396337A |
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