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參數(shù)資料
| 型號： | MC141585 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 畫面疊加 |
| 英文描述： | Rad-Tolerant Class V, Floating Point Digital Signal Processor 429-CFCBGA -55 to 115 |
| 中文描述： | ON-SCREEN DISPLAY IC, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 6/27頁 |
| 文件大?。?/td> | 678K |
| 代理商： | MC141585 |
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MC141585
6
MOTOROLA
PIN DESCRIPTION
VSS(Pin 1)
This is the ground pin for the chip.
PIXin (Pin 2)
This is the Pixel clock input for chip. The MC141585 chip is
driven by this pixel clock for all the logics inside.
NC (Pin 3)
No connection.
VDD (Pin 4)
This is the +5V power pin for the chip.
HSYNC (Pin 5)
This pin inputs a horizontal synchronize signal. It is nega-
tive polarity by default. The leading edge of HSYNC synchro-
nizes its internal horizontal timing. The maximum input ratio
between PIXin/HSYNC should not greater than 1580 for dis-
playing 12X18 font matrix. For displaying 10X18 font matrix,
this ratio should not greater than 1280.
RESET (Pin 6)
An active low signal will reset ROW15 and ROW16 control
registers. Refer to Control Registers section for default set-
tings. A proper RC network have to be tighted to this pin to
ensure the device initialize properly during power up. Refer to
the application diagram.
SDA (Pin 7)
Data and control message are being transmitted to this
chip from a host MCU via M_bus systems. This wire is con-
figurated as a uni-directional data line. (Detailed description
of protocols will be discussed in the M_BUS section).
SCL (Pin 8)
A separate synchronizing clock input from the transmitter
is required for M_Bus protocol. Data is read at the rising edge
of each clock signal.
VDD (Pin 9)
This is the power pin for the digital logic of the chip.
VSYNC (Pin 10)
Similar to Pin 5, this pin inputs a vertical synchronize sig-
nal to synchronize the vertical control circuit. It is negative
polarity by default.
VDD(I) (Pin 11)
This is the voltage supply of RGB outputs when low inten-
sity of Windows/ROW is selected. The RBG output level
would be equal to VDD(I) in this case. Please refer to Row
Attribute/Window registers for more detail. The input voltage
for this pin should be equal to or less than VDD(Pin 17) for
normal operation.
FBKG (Pin 12)
This pin will output a logic high while displaying characters
or windows. It is defaulted to high impedance state after pow-
er on, or when there is no output. An external 10 k
resistor
pulled low is recommended to avoid level toggling caused by
hand effect when there is no output.
B,G,R (Pin 13, 14, 15)
LMOSD2-16 color outputs in CMOS level to the host mon-
itor. These three signals are open drain outputs if 3_STATE
bit is set and the color intensity is inactive. Otherwise, they
are active high push-pull outputs. See “REGISTERS” for
more information. These pins are in high impedance state
after power on.
VSS (Pin 24)
This is the ground pin for the digital logic of the chip.
SYSTEM DESCRIPTION
MC141585 is a full screen memory architecture. Refresh is
done by the built-in circuitry after a screenful of display data
has been loaded in through the serial bus. Only changes to
the display data need to be input afterward.
Serial data, which includes screen mapping address, dis-
play information, and control messages, are being transmit-
ted via M_BUS. Data is first received and saved in the MEM-
ORY MANAGEMENT CIRCUIT in the Block Diagram.
Meanwhile, the LMOSD2-16 is continuously retrieving the
data and putting it into a ROW BUFFER for display and re-
freshing, row after row. During this storing and retrieving cy-
cle, a BUS ARBITRATION LOGIC will patrol the internal traf-
fic, to make sure that no crashes occur between the slower
serial bus receiver and fast ‘screen-refresh’ circuitry. After the
full screen display data is received through one of the serial
communication interface, the link can be terminated if
change on display is not required.
The bottom half of the Block Diagram constitutes the heart
of this entire system. It performs all the LMOSD2-16 func-
tions such as programmable vertical length (from 16 lines to
63 lines), bordering or shadowing, and multiple windowing.
COMMUNICATION PROTOCOLS
M_BUS Serial Communication
This is a two-wire serial communication link that is fully
compatible with the IIC bus system. It consists of SDA bidi-
rectional data line and SCL clock input line. Data is sent from
a transmitter (master), to a receiver (slave) via the SDA line,
and is synchronized with a transmitter clock on the SCL line
at the receiving end. The maximum data rate is limited to
400 kbps.The default chip address is $7A. Please refer to the
IIC-Bus specification for detail timing requirement.
Operating Procedure
Figure 2 shows the M_BUS transmission format. The mas-
ter initiates a transmission routine by generating a START
condition, followed by a slave address byte. Once the ad-
dress is properly identified, the slave will respond with an AC-
KNOWLEDGE signal by pulling the SDA line LOW during the
ninth SCL clock. Each data byte which then follows must be
eight bits long, plus the ACKNOWLEDGE bit, to make up
nine bits together. Appropriate row and column address infor-
mation and display data can be downloaded sequentially in
one of the three transmission formats described in DATA
TRANSMISSION FORMATS SECTION. In the cases of no
ACKNOWLEDGE or completion of data transfer, the master
will generate a STOP condition to terminate the transmission
routine. Note that the OSD_EN bit must be set after all the
display information has been sent in order to activate the
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