參數(shù)資料
型號(hào): MC141585
廠商: MOTOROLA INC
元件分類: 畫面疊加
英文描述: Rad-Tolerant Class V, Floating Point Digital Signal Processor 429-CFCBGA -55 to 115
中文描述: ON-SCREEN DISPLAY IC, PDSO16
封裝: SOIC-16
文件頁數(shù): 15/27頁
文件大小: 678K
代理商: MC141585
MC141585
15
MOTOROLA
Output Programmable Delay Register(Row16, Coln5)
Bit 7-3
X - Don’t care.
Bit 2-0 D2-D0 - These 3 bits define the propagation delay
of R,G,B and FBKG outputs. When D2-D0 are all zero, there
is no additional delay for outputs. Increase these 3 bits will
increase the additional delay. The default setting after
power on is zero.
Figure 13 illustrates the positions of all display characters on
the screen relative to the leading edge of horizontal and vertical
flyback signals. The shaded area indicates the area not inter-
fered by the display characters. Notice that there are two com-
ponents in the equations stated in Figure 13 for horizontal and
vertical delays: fixed delays from the leading edge of HSYNC
and VSYNC signals, regardless of the values of HORD and
VERTD: (47 dots + phase detection pulse width) and one H
scan line for horizontal and vertical delays, respectively; vari-
able delays determined by the values of HORD and VERTD.
Refer to Frame Control Registers COLN 9 and 10 for the defi-
nitions of VERTD and HORD.
When double character width is selected for a row, only the
even-numbered characters will be displayed, as shown in row
2. Notice that the total number of horizontal scan lines in the
display frame is variable, depending on the chosen character
height of each row. Care should be taken while configuring
each row character height so that the last horizontal scan line
in the display frame always comes out before the leading edge
of VSYNC of next frame to avoid wrapping display characters
of the last few rows in the current frame into the next frame.
Figure 14 illustrates the timing of output signals as a function
of window. Line 3 of the two characters is used to illustrate the
timing signals. The shaded area depicts the window area. The
left hand side characters are embodied in a window.
0
1
2
3
4
5
6
7
D0
X
X
D2
X
X
D1
X
Figure 13. Display Frame Format
VSYNC
H
1
R
C
2
3
4
5
6
. . . . . .
1
2
3
0
0
2
2
2
2
d
d
C
C
&
s
&
c
c
c
o
c
c
c
c
c
c
1
variable number of Hscan lines
vertical delay =
VERTD x 4 + 1 H scan lines
h
D
a
d
.
H
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