參數(shù)資料
型號: MC141585
廠商: MOTOROLA INC
元件分類: 畫面疊加
英文描述: Rad-Tolerant Class V, Floating Point Digital Signal Processor 429-CFCBGA -55 to 115
中文描述: ON-SCREEN DISPLAY IC, PDSO16
封裝: SOIC-16
文件頁數(shù): 10/27頁
文件大?。?/td> 678K
代理商: MC141585
MC141585
10
MOTOROLA
Bit 1
CHS - It determines the height of a display sym-
bol. When this bit is set, the symbol is displayed in double
height.
Bit 0
CWS - Similar to bit 1, character is displayed in
double width, if this bit is set.
(III) Window/Control/Frame Register
Window 1 Registers
Row 15 Coln 0
Row 15 Coln 1
Bit 2
WEN - It enables the window 1 generation if this
bit is set.
Bit 1
the color intensity selection for window 1. Setting this bit to 0
means low intensity in this window and R,G,B output voltage
level will be equal to VDD(I). Set this bit to 1 will switch the
supply source of R,G,B back to VDD. Default setting is 0.
Bit 0
W_SHD - Shadowing on Window. Set this bit to
activate the window 1 shadowing. When the window is
active, the right M pixels and lower N horizontal scan lines
will output shadowing. The width/height of window shadow,
number of M/N, is defined in the frame control registers
located at row 15 column 16 and 17 and the shadow color
can be selected in Window Shadow Color Registers at
row16 Column 2 and 3. See the following figure and the
related frame control register for detail.
W_INT - This additional color related bit provides
0
1
2
3
4
5
6
7
ROW END ADDR
MSB
LSB
ROW START ADDR
MSB
LSB
COLN 0
ROW 15
WEN
W_INT
COL START ADDR
MSB
LSB
COLN 1
0
1
2
3
4
5
6
7
ROW 15
W_SHD
Window Shadowing
N Horizontal Lines
M Pixels
M Pixels
WINDOW AREA
N Horizontal Lines
M and N are defined in the
frame control registers
located at row 15 column 16
and column 17.
Shadow color is defined by
by registers located at row 16
column 2 and 3.
NOTE:
Row 15 Coln 2
Bit 2-0 R, G and B - Controls the color of window 1. Refer
to Table 1 for color selection. Window 1 registers occupy
Column 0-2 of Row 15, Window 2 from Column 3-5, Window
3 from 6-8 and Window 4 from 9-11. Window 1 has the high-
est priority, and Window 4 the least. If window over-lapping
occurs, the higher priority window will cover the lower one,
and the higher priority color will take over on the overlap win-
dow area. If the start address is greater than the end
address, this window will not be displayed.
Window 2 Registers
Row 15 Coln 3
Row 15 Coln 4
Bit 2
WEN - It enables the window 2 generation if this
bit is set.
Bit 1
the color intensity selection for window 2. Setting this bit to 0
means low intensity in this window and R,G,B output voltage
level will be equal to VDD(I). Set this bit to 1 will switch the
supply source of R,G,B back to VDD. Default setting is 0.
Bit 0
W_SHD - Shadowing on Window. Set this bit to
activate the window 2 shadowing.
W_INT - This additional color related bit provides
Row 15 Coln 5
Bit 2-0 R, G and B - Controls the color of window 2.Refer
to Table 1 for color selection. Window 1 registers occupy
Column 0-2 of Row 15, Window 2 from Column 3-5, Window
3 from 6-8 and Window 4 from 9-11. Window 1 has the high-
est priority, and Window 4 the least. If window over-lapping
occurs, the higher priority window will cover the lower one,
and the higher priority color will take over on the overlap win-
dow area. If the start address is greater than the end
address, this window will not be displayed.
R
G
COL END ADDR
MSB
LSB
COLN 2
0
1
2
3
4
5
6
7
B
ROW 15
0
1
2
3
4
5
6
7
ROW END ADDR
MSB
LSB
ROW START ADDR
MSB
LSB
COLN 3
ROW 15
COLN 4
ROW 15
WEN
W_INT
COL START ADDR
MSB
LSB
0
1
2
3
4
5
6
7
W_SHD
R
G
COL END ADDR
MSB
LSB
COLN 5
0
1
2
3
4
5
6
7
B
ROW 15
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