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參數(shù)資料
| 型號(hào)： | MC141585 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 畫面疊加 |
| 英文描述： | Rad-Tolerant Class V, Floating Point Digital Signal Processor 429-CFCBGA -55 to 115 |
| 中文描述： | ON-SCREEN DISPLAY IC, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 3/27頁 |
| 文件大?。?/td> | 678K |
| 代理商： | MC141585 |
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MC141585
3
MOTOROLA
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to VSS
NOTE: Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Description section.
AC ELECTRICAL CHARACTERISTICS
(VDD/VDD(I) = 5.0+/-5% V, VSS = 0 V, TA =
0-70C
)
(Voltage Referenced to VSS
)
Symbol
Characteristic
Value
Unit
VDD
Supply Voltage
– 0.3 to + 7.0
V
Vin
Input Voltage
VSS – 0.3 to
VDD + 0.3
V
Id
Current Drain per Pin Excluding VDD and VSS
25
mA
Ta
Operating Temperature Range
0 to 85
°
C
Tstg
Storage Temperature Range
– 65 to + 150
°
C
Symbol
Characteristic
Min
Typ
Max
Unit
tr
tf
Output Signal (R, G, B, and FBKG) Cload = 30 pF
Rise Time (Refer to Figure 1)
Fall Time (Refer to Figure 1)
—
—
3
3
—
—
ns
ns
tsetup
thold
Setup time (Refer to Figure 3)
Programmable Propagation Delay Step = 0
Programmable Propagation Delay Step = 1
Programmable Propagation Delay Step = 2
Programmable Propagation Delay Step = 3
Programmable Propagation Delay Step = 4
Programmable Propagation Delay Step = 5
Programmable Propagation Delay Step = 6
Programmable Propagation Delay Step = 7
Hold time (Refer to Figure 3)
TBD
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—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
tpd
Output Signal (R, G, B and FBKG) Cload = 30 pF
Propagation Delay of output to pixel clock(Figure 2):
Programmable Propagation Delay Step = 0
Programmable Propagation Delay Step = 1
Programmable Propagation Delay Step = 2
Programmable Propagation Delay Step = 3
Programmable Propagation Delay Step = 4
Programmable Propagation Delay Step = 5
Programmable Propagation Delay Step = 6
Programmable Propagation Delay Step = 7
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
—
—
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
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ns
ns
ns
ns
ns
ns
ns
ns
PIXin
Pixel clock input
—
—
80
MHz
FHSYNC
HSYNC Input Frequency
—
—
150K
Hz
FVSYNC
VSYNC Input Frequency
—
—
200
Hz
This device contains protection circuitry to guard
against damage due to high static voltages or
electric fields. However, precautions must be
taken to avoid applications of any voltage higher
than maximum rated voltages to this high-imped-
ance circuit. For proper operation, Vin and Vout
should be constrained to the range VSS
≤
(Vin
or Vout)
≤
VDD.
Unused inputs must always be tied to an appro-
priate logic voltage level (e.g., either VSS or
VDD). Unused outputs must be left open.
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