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94
32015G–AVR32–09/09
AT32AP7001
99. The oscillator has a rather long start-up time of 32768 clock cycles, and no clocks will be
generated in the device during this start-up time.
Note that in static sleep mode the startup counter will start at the negedge of reset and not at the
posedge.
Pulling OSCEN_N high will also disable the 32 KHz oscillator, and a 32 KHz clock must be
applied on the XIN32 pin. No start-up time applies to this clock.
11.5.3
PLL operation
The device contains two PLL’s, PLL0 and PLL1. These are disabled by default, but can be
enabled to provide high frequency source clocks for synchronous or generic clocks. The PLL’s
can take either Oscillator 0 or 1 as clock source. Each PLL has an input divider, which divides
the source clock, creating the reference clock for the PLL. The PLL output is divided by a user-
defined factor, and the PLL compares the resulting clock to the reference clock. The PLL will
adjust its output frequency until the two compared clocks are equal, thus locking the output fre-
quency to a multiple of the reference clock frequency.
When the PLL is switched on, or when changing the clock source or multiplication or division
factor for the PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for
the digital logic is automatically masked when the PLL is unlocked, to prevent connected digital
logic from receiving a too high frequency and thus become unstable.
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