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參數資料
| 型號： | MB91F482PMC-GE1 |
| 廠商： | Fujitsu Semiconductor America Inc |
| 文件頁數： | 18/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 256KB FLASH 100-LQFP |
| 標準包裝： | 1 |
| 系列： | FR MB91480 |
| 核心處理器： | FR60 RISC |
| 芯體尺寸： | 32-位 |
| 速度： | 80MHz |
| 連通性： | I²C，FIFO，SIO |
| 外圍設備： | DMA，PWM，WDT |
| 輸入/輸出數： | 77 |
| 程序存儲器容量： | 256KB（256K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 數據轉換器： | A/D 14x8/10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤 |
| 其它名稱： | 865-1097 |
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MB91470/480 Series
25
■ HANDLING DEVICES
Preventing latch-up
Latch-up phenomenon may occur with CMOS IC, when a voltage higher than VCC or lower than VSS is applied
to either the input or output terminals, or when a voltage is applied between VCC pin and VSS pin that exceeds the
rated voltage. When latch-up occurs, a significant power-supply current surge results, which may damage some
elements due to the excess heat, so great care must be taken to ensure that the maximum rating is never
exceeded during use.
Treatment of unused input pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a
pull-up or pull-down resistor.
Power pins
In products with multiple VCC and VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to the same potential power
supply and a ground line externally to lower the electro-magnetic emission level, to prevent abnormal operation
of strobe signals caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1
F as a bypass capacitor between VCC
and VSS near this device.
Crystal oscillator circuit
Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that X0,
X1, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the
device as possible.
It is strongly recommended to design the PC board artwork with the X0 and X1pins surrounded by ground plane
because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate the
oscillational characteristics of the crystal and this device.
About mode pins (MD0 to MD2)
These pins should be connected directly to VCC pin or VSS pin.
Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between
the mode pins and power supply or GND pins is as short as possible and the connection impedance is low,
when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Operation at start-up
Be sure to execute setting initialized reset (INIT) with INITX pin immediately after start-up.
Immediately after that, also, hold the "L"-level input to the INITX pin for the stabilization wait time required for the
oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit and the stabilization wait
time for the regulator (For INIT via the INITX pin, the oscillation stabilization wait time setting is initialized to the
minimum value).
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