參數(shù)資料
型號(hào): MB91F482PMC-GE1
廠商: Fujitsu Semiconductor America Inc
文件頁數(shù): 41/94頁
文件大小: 0K
描述: IC MCU 256KB FLASH 100-LQFP
標(biāo)準(zhǔn)包裝: 1
系列: FR MB91480
核心處理器: FR60 RISC
芯體尺寸: 32-位
速度: 80MHz
連通性: I²C,F(xiàn)IFO,SIO
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 77
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 14x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
其它名稱: 865-1097
48
32015G–AVR32–09/09
AT32AP7001
different Input Selection Modes. See Section 8.5 ”Input Pixel Selector” on page 27 for a description of the Input Pixel
Selector.
OFFSET_FRAC_BITS: Offset Fractional Bits
Specifies the number of fractional bits in the fixed-point offsets input to each VMU. Must be in the range from 0 to
COEFF_FRAC_BITS. Other values gives undefined results.This value is used for scaling the OFFSETn values before
being input to VMUn so that the offset will have the same fixed-point format as the outputs from the multiplication stages
before performing the vector addition in the VMU.
COEFF_FRAC_BITS: Coefficient Fractional Bits
Specifies the number of fractional bits in the fixed-point coefficients input to each VMU. Must be in the range from 0 to 11,
since at least one bit of the coefficient must be used for the sign. Other values gives undefined results.
COEFF_FRAC_BITS is used in the Output Pixel Inserter to scale the fixed-point results from the VMUs back to unsigned 8-
bit integers.
Table 8-3.
Input Selection Modes
ISM
Mode
0
Transformation Mode
VMU0, VMU1 and VMU2 get the same pixel inputs. These three pixels can be
freely selected from the INPIXn registers.
0
1
Horizontal Filter Mode
Pixel triplets are selected for input to each of the VMUs by addressing
horizontal pixel triplets from the INPIXn registers.
1
0
Vertical Filter Mode
Pixel triplets are selected for input to each of the VMUs by addressing vertical
pixel triplets from the INPIXn registers.
1
Reserved
N.A
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