參數(shù)資料
型號(hào): MB91F482PMC-GE1
廠商: Fujitsu Semiconductor America Inc
文件頁(yè)數(shù): 26/94頁(yè)
文件大?。?/td> 0K
描述: IC MCU 256KB FLASH 100-LQFP
標(biāo)準(zhǔn)包裝: 1
系列: FR MB91480
核心處理器: FR60 RISC
芯體尺寸: 32-位
速度: 80MHz
連通性: I²C,F(xiàn)IFO,SIO
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 77
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 14x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤(pán)
其它名稱: 865-1097
MB91470/480 Series
32
■ MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and mode data to set the operation mode.
1.
Mode Pins
The MD2 to MD0 pins specify how the mode vector fetch and reset vector fetch is performed.
Settings other than those shown in the following table are prohibited.
2.
Mode data
The data that is written to the internal mode register (MODR) by the mode vector fetch is called mode data.
After the mode register is set, the device runs in the operating mode specified by this register.
The mode data is set by all of the reset sources. User programs cannot set the mode register.
<Details of mode data description>
[bit 23 to bit 19] Reserved bits
Be sure to set these bits to “00000B”.
Operation is not guaranteed if these bits are set to a value other than “00000B”.
[bit 18] ROMA (Internal Flash/ROM enable bit)
This bit configures whether the internal Flash/ROM area (8 0000H to F FFFFH) is enabled.
Mode Pins
Mode name
Reset vector
access area
Remarks
MD2
MD1
MD0
0
Internal ROM mode vector
Internal
0
1
External ROM mode vector
External
The bus width is set
by mode register.
ROMA
Function
Remarks
0
External ROM mode
Internal Flash/ROM area (8 0000H to F FFFFH) is used as an external area.
1
Internal ROM mode
Internal Flash/ROM area (8 0000H to F FFFFH) is enabled.
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
0
ROMA
WTH1
WTH0
Operation mode setting bits
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