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| 型號(hào)： | MB91314APMC-GE1 |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁(yè)數(shù)： | 63/73頁(yè) |
| 文件大?。?/td> | 810K |
| 代理商： | MB91314APMC-GE1 |
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MB91314A Series
66
At slave mode operating
(VDDE
= 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V, VSS = 0 V, Ta = 10 °C to + 70 °C)
*1 : M = Resource clock cycle (ns)
*2 : A high-speed mode I2C bus device can be used for a typical mode I2C bus system as long as the device satisfies
a requirement of “tSUDAT
≥ 250 ns”.
When a certain device does not extend the “L” period of the SCL signal, the next data must be output to the
SDA line within 1250 ns (maximum SDA/SCL rise time
+ tSUDAT) in which the SCL line is released.
*3 : For use at over 100 kHz, set the resource clock to 6 MHz or higher.
*4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines, respectively.
Parameter
Symbol Conditions
Typical mode
High-speed
mode*3
Unit
Remarks
Min
Max
Min
Max
SCL clock frequency
fSCL
R
= 1 k,
C
= 50 pF*4
0
100
0
400
kHz
“L” period of SCL clock
tLOW
4.7
1.3
s
“H” period of SCL clock
tHIGH
4.0
0.6
s
SCL
↓ → SDA output delay
time
tDLDAT
5
× M*1
5
× M*1 ns
Bus free time between
“STOP condition” and
“START condition”
tBUS
4.7
1.3
s
SDA data input hold time
(vs. SCL
↓)
tHDDAT
2
× M*1
2
× M*1
s
SDA data input setup time
(vs. SCL
↑)
tSUDAT
250
100*2
ns
Repeated START condi-
tion setup time SCL
↑ →
SDA
↓
tSUSTA
4.7
0.6
s
Repeated START condi-
tion hold time SDA
↓ →
SCL
↓
tHDSTA
4.0
0.6
s
The first clock
pulse is generated
after this.
STOP condition setup time
SCL
↑ → SDA ↑
tSUSTO
4.0
0.6
s
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