參數(shù)資料
型號(hào)： MB91314APMC-GE1
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 33 MHz, RISC MICROCONTROLLER, PQFP120
封裝： 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120
文件頁數(shù)： 18/73頁
文件大小： 810K
代理商： MB91314APMC-GE1
MB91314A Series
25
2.
Internal architecture
The FR family of CPUs has a Harvard architecture in which the instruction bus and data bus are separated.
The 32-bit
16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interface between the
CPU and peripheral resources.
The Harvard
Princeton bus converter is connected to both of the I-bus and D-bus, providing an interface
between the CPU and the bus controller.
32
24
16
FRex CPU
D-bus
I-bus
F-bus
R-bus
Peripheral resources
Internal I/O
Bus converter
Address
Data
bus converter
16-bit
32-bit
External address
External data
Princeton
bus
converter
I data
Harvard
I address
D data
D address
Data RAM
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