參數(shù)資料
型號(hào)： MB91101APF
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 91/99頁
文件大小： 935K
代理商： MB91101APF
MB91101/MB91101A
91
(16) DMA Controller Timing
(VCC5 = 5.0 V
±10%, VSS = AVSS = 0.0 V, TA = 0°C to +70°C)
(VCC5 = VCC3 = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = 0
°C to +70°C)
tCYC (a cycle time of peripheral system clock): Refer to “(2) Clock Output Timing.”
Parameter
Symbol
Pin name
Condition
Value
Unit
Remarks
Min
Max
DREQ input pulse width tDRWH
DREQ0 to DREQ2
—
2
× tCYC
—ns
DACK delay time
(Normal bus)
(Normal DRAM)
tCLDL
CLK,
DACK0 to DACK2
—6
ns
tCLDH
CLK,
DACK0 to DACK2
—6
ns
EOP delay time
(Normal bus)
(Normal DRAM)
tCLEL
CLK,
EOP0 to EOP2
—6
ns
tCLEH
CLK,
EOP0 to EOP2
—6
ns
DACK delay time
(Single DRAM)
(Hyper DRAM)
tCHDL
CLK,
DACK0 to DACK2
—n/2
× tCYC
ns
tCHDH
CLK,
DACK0 to DACK2
—6
ns
EOP delay time
(Single DRAM)
(Hyper DRAM)
tCHEL
CLK,
EOP0 to EOP2
—n/2
× tCYC
ns
tCHEH
CLK,
EOP0 to EOP2
—6
ns
CLK
DREQ0 to DREQ2
VOH
VIH
VOL
VOH
DACK0 to DACK2
EOP0 to EOP2
(Normal bus)
(Normal DRAM)
DACK0 to DACK2
EOP0 to EOP2
(Single DRAM)
(Hyper DRAM)
tCYC
tDRWH
tCLDL
tCLEL
tCHDL
tCHEL
tCLDH
tCLEH
tCHDH
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