參數(shù)資料
型號(hào)： MB91101APF
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 30/99頁(yè)
文件大?。?/td> 935K
代理商： MB91101APF
MB91101/MB91101A
36
s
s PERIPHERAL RESOURCES
1.
I/O Ports
There are 2 types of I/O port register structure; port data register (PDR0 to PDRF) and data direction register
(DDR0 to DDRF), where bits PDR0 to PDRF and bits DDR0 to DDRF corresponds respectively. Each bit on
the register corresponds to an external pin. In port registers input/output register of the port configures input/
output function of the port, while corresponding bit (pin) configures input/output function in data direction regis-
ters. Bit “0” specifies input and “1” specifies output.
For input (DDR = “0”) setting;
PDR reading operation: reads level of corresponding external pin.
PDR writing operation: writes set value to PDR.
For output (DDR = “1”) setting;
PDR reading operation: reads PDR value.
PDR writing operation: outputs PDR value to corresponding external pin.
Block diagram
PDR
DDR
(Port data register)
(Data direction register)
Resource output enable
Resource output
1
0
1
0
PDR read
Resource input
Pin
Data
bus
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB91101APFR-G-JNE1 制造商:FUJITSU 功能描述:
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