參數(shù)資料
型號(hào)： MB91101APF
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 48/99頁
文件大小： 935K
代理商： MB91101APF
MB91101/MB91101A
52
9.
Interrupt Controller
The interrupt controller processes interrupt acknowledgments and arbitration between interrupts.
Block diagram
R-bus
LEVEL0*4
IM
INT0*2
OR
Priority judgment
NMI
NMI processing
(DLYIRQ)
RI00
RI47
DLYI*1
Level judgment
ICR00
ICR47
Vector judgment
4
5
6
Level
vector
generation
HLDREQ
cancel
request
LEVEL4 to
HLDCAN*3
VCT0*5
VCT5 to
*6
*7
*1: DLYI stands for delayed interrupt module (delayed interrupt generation block) (refer to the section “11.
Delayed Interrupt Module” for detail).
*2: INT0 is a wake-up signal to clock control block in the sleep or stop status.
*3: HLDCAN is a bus release request signal for bus masters other than CPU.
*4: LEVEL4 to LEVEL0 are interrupt level outputs.
*5: VCT5 to VCT0 are interrupt vector outputs.
*6: IM is an interrupt mask signal.
*7: RI00 to RI47 are interrupt request signals.
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