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參數(shù)資料
| 型號： | MB90M407PF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 24/68頁 |
| 文件大小： | 1486K |
| 代理商： | MB90M407PF |
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MB90M405 Series
30
DS07-13718-3E
Counter Operation
Reload mode
When the 16-bit down counter underflows (“0000H” to “FFFFH”) , the value of the 16-bit reload register (TMRLR)
is loaded into the 16-bit down counter, and count operation is conducted. In addition, when an underflow occurs
an interrupt request is output, so this can also be used as an interval timer. It is possible to output the inverted
toggle waveform from the TO pin with each underflow.
φ : Machine clock frequency
Values in parentheses ( ) are when machine clock frequency is 16 MHz.
One-shot mode
When the 16-bit down counter underflows (“0000H” to “FFFFH”) , count operation is halted.
Reference :
16-bit reload timer 0 can be used to create the UART baud rate.
16-bit reload timer 1 can be used as the start trigger for the A/D converter.
16-bit Reload Timer Interrupts and EI2OS
When the 16-bit down counter underflows (“0000H” to “FFFFH”) , an interrupt request is output.
: Available if interrupt factors sharing ICR are not used
Count Clock
Count Clock Cycle
Interval Time
Internal Count Clock
21/
φ (0.125 s)
0.125
s to 8.192 ms
23/
φ (0.5 s)
0.5
s to 32.768 ms
25/
φ (2.0 s)
2.0
s to 131.1 ms
External Count Clock
23/
φ+ (0.5 s)
0.5
s +
Channel
Interrupt
No.
Interrupt Control Register
Vector Table Address
EI2OS
Register Name
Address
Lower
Upper
Bank
16-bit reload timer 0 #23 (17H)
ICR06
0000B6H
FFFFA0H
FFFFA1H
FFFFA2H
16-bit reload timer 1 #24 (18H)
FFFF9CH
FFFF9DH
FFFF9EH
16-bit reload timer 2 #21 (15H)
ICR05
0000B5H
FFFFA8H
FFFFA9H
FFFFAAH
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