參數(shù)資料
型號(hào): MB90F574
廠商: Fujitsu Limited
英文描述: Octal Bus Transceivers And Registers With 3-State Outputs 28-LCCC -55 to 125
中文描述: 16位微控制器專有
文件頁數(shù): 40/135頁
文件大?。?/td> 2504K
代理商: MB90F574
40
MB90570 Series
3. Watchdog Timer
The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when
the counter is not cleared for a preset period of time.
(1) Register Configuration
(2) Block Diagram
Watchdog timer control register (WDTC)
Address
0000A8
H
bit 15 . . . . . . . . . . . .
PONR STBR WRST ERST
SRST
WTE
WT1
WT0
(TBTC)
R : Read only
W: Write only
X : Indeterminate
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
R
R
R
R
W
W
W
Initial value
XXXXXXXX
B
HCLK: Oscillation clock
PONR STBR WRST ERST SRST WTE
WT1
WT0
Watchdog timer control register (WDTC)
Start sleep mode
Start hold status
Start stop mode
CLR and start
Watchdog timer
Overflow
To internal reset
generation circuit
Counter clear
control circuit
Count clock
selector
2-bit
counter
Watchdog timer
reset generation
circuit
Clear
Divided-by-2
of HCLK
(Timebase timer counter)
×
2
1
×
2
2
. . .
×
2
8
×
2
9
×
2
10
×
2
11
×
2
12
×
2
13
×
2
14
×
2
15
×
2
16
×
2
17
×
2
18
CLR
2
4
CLR
相關(guān)PDF資料
PDF描述
MB90V570 16-bit Proprietary Microcontroller
MB90V570A 16-bit Proprietary Microcontroller
MB90F574APFF 16-bit Proprietary Microcontroller
MB90F574APFV 16-bit Proprietary Microcontroller
MB90F574A Octal Bus Transceivers And Registers With 3-State Outputs 24-CFP -55 to 125
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