參數(shù)資料
型號: MB90F574/APFF
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, MICROCONTROLLER, PQFP120
封裝: PLASTIC, LQFP-120
文件頁數(shù): 82/120頁
文件大?。?/td> 1834K
代理商: MB90F574/APFF
MB90570 Series
64
11. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks for development on a real-time
operating system (REALOS series). The module can be used to generate softwarewise generates hardware
interrupt requests to the CPU and cancel the interrupts.
This module does not conform to the extended intelligent I/O service (EI2OS).
(1) Register Configuration
The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this
register with “1” generates a delay interrupt request. Programming this register with “0” cancels a delay interrupt
request. Upon a reset, an interrupt is canceled. The reserved bit area can be programmed with either “0” or “1”.
For future extension, however, it is recommended that bit set and clear instructions be used to access this register.
(2) Block Diagram
Delayed interrupt factor generation/cancellation register (DIRR)
Address
00009FH
bit 7
bit 0
————
R0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
............
(PACSR)
————
R/W
Initial value
------- 0 B
R/W:Readable and writable
—:Reserved
Note: Upon a reset, an interrupt is canceled.
Delayed interrupt factor generation/
cancellation register (DIRR)
*: Interrupt number
S factor
R latch
——
———
R0
Internal data bus
Interrupt request signal
#42*
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