參數(shù)資料
型號： MB90F574/APFF
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, MICROCONTROLLER, PQFP120
封裝： PLASTIC, LQFP-120
文件頁數(shù)： 111/120頁
文件大?。?/td> 1834K
代理商： MB90F574/APFF
MB90570 Series
90
(6) Bus Read Timing
(AVCC = VCC = 5.0 V
±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
* : For tCP (internal operating clock cycle time), refer to “(3) Clock Timings.”
Parameter
Symbol
Pin name
Condition
Value
Unit Remarks
Min
Max
ALE pulse width
tLHLL
ALE
—
1 tCP*/2 – 20
—
ns
Effective address
→
ALE
↓ time
tAVLL
ALE,
A23 to A16,
AD15 to AD00
1 tCP*/2 – 20
—
ns
ALE
↓ → address
effective time
tLLAX
ALE,
AD15 to AD00
1 tCP*/2 – 15
—
ns
Effective address
→
RD
↓ time
tAVRL
RD,
A23 to A16,
AD15 to AD00
1 tCP* – 15
—
ns
Effective address
→
valid data input
tAVDV
A23 to A16,
AD15 to AD00
—5 tCP*/2 – 60
ns
RD pulse width
tRLRH
RD
3 tCP*/2 – 20
—
ns
RD
↓ → valid data input
tRLDV
RD,
AD15 to AD00
—3 tCP*/2 – 60
ns
RD
↑ → data hold time
tRHDX
RD,
AD15 to AD00
0—
ns
RD
↑ → ALE ↑ time
tRHLH
ALE, RD
1 tCP*/2 – 15
—
ns
RD
↑ → address
effective time
tRHAX
ALE,
A23 to A16
1 tCP*/2 – 10
—
ns
Effective address
→
CLK
↑ time
tAVCH
CLK,
A23 to A16,
AD15 to AD00
1 tCP*/2 – 20
—
ns
RD
↓ → CLK ↑ time
tRLCH
CLK, RD
1 tCP*/2 – 20
—
ns
ALE
↓ → RD ↓ time
tALRL
ALE, RD
1 tCP*/2 – 15
—
ns
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