參數(shù)資料
型號： MB90F372PMT-G
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP144
封裝： 0.40 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù)： 101/153頁
文件大?。?/td> 2503K
代理商： MB90F372PMT-G
MB90370 Series
51
4.
Watchdog timer
The watchdog timer is a 2-bit counter that uses the timebase timer’s supply clock as the count clock. After
activation, if the watchdog timer is not cleared within a given period, the CPU will be reset.
Features of watchdog timer :
Reset CPU at four different time intervals
Status bits to indicate the reset causes
(1) Register configuration of watchdog timer
(2) Block diagram of watchdog timer
Address: 0000A8H
76
5
4
3
2
1
0
Watchdog Timer Control Register
WDTC
Bit number
R
X
R
X
R
X
R
X
W
1
W
1
W
1
Initial value
Read/write
PONR
WRST
ERST
SRST
WTE
WT1
WT0
PONR
WRST ERST SRST WTE
WT1
WT0
Watchdog timer control register (WDTC)
X21 X22
X28 X29 X210 X2
11
X213
X212
X215
X214
Counter
clear control
circuit
Count
clock
selector
2-bit
counter
Watchdog
reset
generat
or
X21 X22
X210 X211
X213
X212
X215
X214
...
.........
HCLK: Oscillation clock
One-half of HCLK
(Timebase timer counter)
Watch timer counter
Sub-clock divide by 4
CLK
Watchdog timer
CLR
Activation with CLR
Overflow
To the
internal
reset
generator
WDCS (from watch timer
control register, WTC)
2
Start of watch mode
Start of sleep mode
Start of stop mode
reset generation
X216 X217 X218
4
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