參數(shù)資料
型號(hào)： MB89F051PMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP64
封裝： 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 9/40頁(yè)
文件大?。?/td> 931K
代理商： MB89F051PMC
MB89051 Series
DS07-12551-3E
17
The RP points to the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule shown next.
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at the time of an interrupt.
H flag
: The flag is set to “1” when an arithmetic operation results in a carry from bit 3 to bit 4 or in a borrow
from bit 4 to bit 3. The bit is cleared to “0” in other instances.The flag is for decimal adjustment
instructions; do not use for other than additions and subtractions.
I flag
: Interrupt is enabled when this flag is set to “1.” Interrupt is disabled when this flag is set to “0.” The
flag is set to “0” when reset.
IL1, 0
:
Indicates the level of the interrupt currently enabled.An interrupt is processed only if its level is
higher than the value this bit indicates.
IL1
IL0
Interrupt level
High-low
00
1
Higher
Lower = no interruption
01
10
2
11
3
N flag
: The flag is set to “1” when an arithmetic operation results in setting of the MSB to “1” or is cleared
to “0” when the MSB is set to “1.”
Z flag
: The flag is set to “1” when an arithmetic operation results in “0” or is set to “0” in other instances.
V flag
: The flag is set to “1” when an arithmetic operation results in two’s complement overflow or is
cleared to “0” if no overflow occurs.
C flag
: The flag is set to “1” when an arithmetic operation results in a carry from bit 7 or in a borrow to bit
7. The flag is cleared to “0” if neither of them occurs. In the case of a shift instruction, the flag is
set to the shift-out value.
Rule for Conversion of Actual Addresses in the General-purpose Register Area
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
b0
A7
A6
A5
A4
A3
A2
A1
A0
A15 A14 A13 A12 A11 A10
A9
A8
Generated address
RP higher bits
OP code lower bits
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