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參數(shù)資料
| 型號： | MB86612PBT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SERIAL COMM CONTROLLER, PBGA120 |
| 封裝： | PLASTIC, FBGA-120 |
| 文件頁數(shù)： | 40/40頁 |
| 文件大?。?/td> | 574K |
| 代理商： | MB86612PBT |
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9
MB86612
s PIN DESCRIPTION
1. 1394 Interface
2. Isochronous-data Interface
(Continued)
Pin name
I/O
Function
TPA0
I/O
Cable port 0 TPA positive signal I/O pin
TPA0
I/O
Cable port 0 TPA negative signal I/O pin
TPB0
I/O
Cable port 0 TPB positive signal I/O pin
TPB0
I/O
Cable port 0 TPB negative signal I/O pin
TPA1
I/O
Cable port 1 TPA positive signal I/O pin
TPA1
I/O
Cable port 1 TPA negative signal I/O pin
TPB1
I/O
Cable port 1 TPB positive signal I/O pin
TPB1
I/O
Cable port 1 TPB negative signal I/O pin
TPBIAS0
O
Cable port 0 common voltage reference voltage output pin
TPBIAS1
O
Cable port 1 common voltage reference voltage output pin
RO0
O
Connect to GND through 4.7 k
resistance
RO1
O
Connect to GND through 4.7 k
resistance
Pin name
I/O
Function
ICLK
I
Isochronous data interface CLK signal input pin (DC to 16 MHz).
Note: When this clock is stopped, transfer is stopped. Also the “Data FIFO init
(63h)” instruction (operand: 21) is invalid.
IDIR
I
Isochronous transfer sending/receiving switching signal input pin.
0 input: Clear ISO FIFO, go to sending mode.
Sending starts after receiving 1 packet of data.
1 input: Clear ISO FIFO, go to receiving mode. If a ‘1’ signal is entered during
packet sending, receiving mode begins after sending of the current packet.
The ILWRE signal is asserted after receiving 1 packet.
Note: This signal should normally be left at ‘1’, and switched to ‘0’ only when
sending.
ILWRE
O
Isochronous FIFE access enable signal output pin.
Sending: Asserted when 1 or more empty source packets are present in ISO
FIFO.
When negated, the data output up to the leading edge for the next ICLX.
Receiving: Asserted when receiving of 1 source packet of data is completed.
Negate conditions for this signal are determined by the ilwre-mode bit (bit 11) in
the mode-control register.
ID7 to ID0
I/O
Isochronous transfer data input/output bits. (MSB is ID7, LSB is ID0)
IV
I
ID7 to ID0 enable signal input pin.
Sending: While this signal is active, data from the ID7 to ID0 pins is loaded into
ISO FIFO memory at the rising edge of the ICLK signal.
Receiving: While this signal is active, data from ISO FIFO memory is sent to the
ID7 to ID0 pins. Data is switched at the falling edge of the ICLK signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86612PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Bus Controller (for MPEG, DVC) |
| MB86613 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Open HCI Controller |
| MB86613PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Open HCI Controller |
| MB86613PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Open HCI Controller |
| MB86613S | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE1394 Open HCI Controller |
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