參數(shù)資料
型號(hào): MB86612PBT
元件分類: 微控制器/微處理器
英文描述: SERIAL COMM CONTROLLER, PBGA120
封裝: PLASTIC, FBGA-120
文件頁(yè)數(shù): 22/40頁(yè)
文件大?。?/td> 574K
代理商: MB86612PBT
29
MB86612
(2) End Sending Operation
* : The MB86612 operates in ‘negate mode’, in which the ILWRE signal is negated for each source packet received,
as well as ‘a(chǎn)ssert mode’, in which the ILWRE signal is continuously asserted as long as ISO sending and receiving
FIFO writing are enabled. The above timing chart shows operation in negate mode. If there one or more packets
of empty space are present in the sending or receiving FIFO area, the ILWRE signal is again asserted.Note that
even in assert mode, if writing to the ISO sending or receiving FIFO areas is disabled, the ILWRE signal is negated
according to the timing shown above, and re-asserted when writing is again enabled.
Parameter
Symbol
Value
Unit
Min.
Max.
ICLK rise to ILWRE rise
tCHLH
—40
ns
ILWRE rise to IV rise
tLHVH
1 ticlk + 10
ns
ILWR negate time*
tLWH
2 ticlk – 10
ns
ICLK
IDIR
ILWRE
IV
ID7 to ID0
N - 2
N
1
tCHLH
tLWH
tLHVH
N - 1
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