參數(shù)資料
型號: MB86612PBT
元件分類: 微控制器/微處理器
英文描述: SERIAL COMM CONTROLLER, PBGA120
封裝: PLASTIC, FBGA-120
文件頁數(shù): 26/40頁
文件大?。?/td> 574K
代理商: MB86612PBT
32
MB86612
(2) End Receiving Operation
*1: The MB86612 operates in ‘negate mode’, in which the ILWRE signal is negated for each source packet received,
as well as ‘a(chǎn)ssert mode’, in which the ILWRE signal is continuously asserted as long as ISO sending and
receiving FIFO writing are enabled. The above timing chart shows operation in negate mode. If there one or
more packets of empty space are present in the sending or receiving FIFO area, the ILWRE signal is again
asserted.Note that even in assert mode, if writing to the ISO sending or receiving FIFO areas is disabled, the
ILWRE signal is negated according to the timing shown above, and re-asserted when writing is again enabled.
*2: The TS (in MPEG mode) and IERR signals are negated in synchronization with the ILWRE signal.
Parameter
Symbol
Value
Unit
Min.
Max.
ICLK rise to ILWRE rise
tCHLH
—40
ns
ILWRE rise to IV rise
tLHVH
1 ticlk + 10
ns
Final data output disable time
tVHIDX
—20
ns
ILWRE negate time*1
tLWH
2 ticlk – 10
ns
ICLK
IDIR
ILWRE
IERR*
TS*
IV
ID7 to ID0
Hi
Z
N - 2
N - 1
N
tCHLH
tLWH
tLHVH
tVHIDX
2
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參數(shù)描述
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