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參數(shù)資料
| 型號(hào)： | MB86612 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 98.304M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 33/35頁 |
| 文件大?。?/td> | 552K |
| 代理商： | MB86612 |
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MB86612
7
ISOCHRONOUS INTERFACE
Name of pin
I/O
I
O
I/O
I
I/O
O
ICLK
IDIR
ILWRE
ID7 to 0
IV
TS
IERR
CTR
OCLK
Function
Clock input pin for isochronous interface (DC to 16MHz) When the clock stops the data trans-
fer also stops and ”data- FIFO init” instruction (with operand : 21h) is invalid.
Input pin for transmission/reception (data direction) changeover signal
When ”0” :
clears the FIFO and be ready for transmission. It starts the transmission after
receiving 1 packet data.
When ”1” :
clears the FIFO and be ready for the reception. It asserts ILWRE signal by a
receipt of 1 packet data.
Note: This signal should normally retain ”1” and turn to ”0” _only_ when the data transmission
is performed.
Access permit signal to isochronous FIFO
At transmission: This signal becomes active if there is any space to store one or more source
packet data in the FIFO. At the negation of this signal, the data for the next
rising edge of ICLK are received.
At reception:
The signal is asserted at the completion of 1 source packet data reception.
The negate condition for this signal follows the ilwre- mode bit setting in the
mode control register. Refer to the register description.
Input/output pins of isochronous transfer data (MSB: ID7, LSB: ID0)
ENABLE signal of ID7 to 0.
At transmission: Fetches data into the FIFO by a rising edge of ICLK while this signal is active.
At reception:
Sends data in the FIFO to the ID7- ID0 by the active signal of this pin. After that,
the data changes synchronized with the falling edge of ICLK.
At transmission (input); This signal serves as time stamp trigger signal input for DVC mode.
The transmit time stamp is generated by adding the cycle- timer value when this signal is as-
serted with the transmit offset value. This signal is not used in MPEG mode.
At receipt (output); It serves as a time- stamp matching signal. For MPEG mode, this signal is
negated after reading out one source packet data. For DVC mode, this signal is asserted for
32tICLK (32 cycles of ICLK). This signal is not output when an error occurs on the received
isochronous packet.
Isochronous packet error signal output. When an error is detected on the received isochrono-
us packet, this signal is asserted. Because TS pin does not output any signal when an error
occurs on the received isochronous packet, the received packet should be read out with this
signal as the triggered signal. Please note that this signal is not output in case any kinds of
error that discard the received packet.
Cycle Timer Update output pin. When the value for the cycle timer is updated, CTR outputs
the signal..
This signal’s output is optional per the CTR bit of ”mode- control register”.
Clock Output pin for the Cycle Timer (24.576MHz). Whether or not this clock signal is output is
optional per the CTR bit setting of ”mode- control register”.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86612PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Bus Controller (for MPEG, DVC) |
| MB86612PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Bus Controller (for MPEG, DVC) |
| MB86613 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Open HCI Controller |
| MB86613PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Open HCI Controller |
| MB86613PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IEEE 1394 Open HCI Controller |
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