參數(shù)資料
型號(hào): MB86612
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 98.304M bps, SERIAL COMM CONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 3/35頁
文件大小: 552K
代理商: MB86612
MB86612
11
BLOCK FUNCTION
<Physical layer>
Supports asynchronous transfer and isochronous transfer under IEEE 1394 cable circumstance
98.304Mb/s transfer speed
Two ports for analog transceiver/receiver, with bus status monitor, initialization, arbitration and encode/decode functions for data transmission/
reception
<Link layer>
Controls generation and transfer of standard packet in compliance with IEEE 1394
Generates and checks 32-bits CRC for data and header
Incorporates 32-bits cycle timer register and cycle master function
<Transmission/Reception FIFO>
Incorporates 4KB FIFO for isochronous smoothing and the rate conversion
Incorporates 128B FIFOs for both transmission/reception as asynchronous transfer
<Packet Process>
For transmission, it packetizes the header, data, and CRC sections. CRC is automatically generated and added.
For reception, it isolates the bus packet into the header and data sections, and discards the CRC section.
<Dedicated Transaction Circuit>
Packetizes the dedicated format from data interface pin and reconstructs a receive data to data interface pin with transmission/reception packet
processing unit for transfer
Controls a detecting and executing of application specific command input to asynchronous data interface pin.
<Various Registers>
These registers are composed of the MB86612 control register, transfer parameter register, AV/C protocol register, and various CSRs. The
on- chip CSRs support the Isochronous Resource Manager.
<PLL circuit>
Generates internal operation clock and transfer clock from reference clock generated by crystal oscillator circuit. Reference oscillation frequen-
cy: 8.192 MHz
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