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參數(shù)資料
| 型號(hào)： | MB86391 |
| 廠商： | Fujitsu Limited |
| 英文描述： | MPEG2 1chip Audio/Video Encoder |
| 中文描述： | 的MPEG2 1chip音頻/視頻編碼器 |
| 文件頁(yè)數(shù)： | 9/69頁(yè) |
| 文件大小： | 847K |
| 代理商： | MB86391 |
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FUJITSU LIMITED
Proprietary and Confidential
MB86391 12, November 2001
Product Specification
Rev. 1.1
5
1.4 Block Diagram
Fig. 1.4 shows a block outline diagram of this LSI and Table 1.4 lists the functional overviews of major blocks.
Fig. 1.4 : MB86391 block diagram
Table 1.4 : Overview of major block functions
Block name
Functional overview
Video encoder
Audio encoder
Multiplexer
Encodes video data input from the TBC controller to create video streams.
Encodes audio data input from outside to create audio streams.
Multiplexes video and audio streams generated by video and audio
encoders to generate 8bit parallel stream data for output to outside.
Controls the entire MB86391 using dedicated firmware.
Stores video data input from outside in an external SDRAM and then nput it
to the video encoder. The TBC (Time Base Corrector) function is
accomplished by buffering video data in the SDRAM.
Arbitrates SDRAM and MB86391 internal register access requests from
MB86391 internal blocks and external master devices. Also used as the
command interface with the host.
Downloads dedicated firmware to the external SDRAM via this interface at
the time of serial booting. Also used as a command interface with the host.
Converts the format of video streams the video encoder has generated and
outputs to the multiplexer.
Controls DMA transfer among MB86391 blocks and external SDRAMs.
Stores the boot program for the internal controller.
Controller
TBC controller
Host/SDRAM interface controller
Serial interface
controller
Video PES converter
DMA controller
Boot ROM
Video encoder
Audio encoder
Controller
(32bit RISC
processor)
Multiplexer
TBC controller
Serial interface
controller
Boot
ROM
Host/SDRAM
interface
controller
SRAM
(8k
×
8)
MB86391
Serial interface
Host/SDRAM
interface
Video encoding
SDRAM
interface
Audio input interface
Video input interface
Bit stream output
port
PLL
Clock input
(27MHz)
27MHz
54MHz
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